56 	ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);  in ravb_modify()
98 		ravb_write(ndev, GECMR_SPEED_100, GECMR);  in ravb_set_rate()
101 		ravb_write(ndev, GECMR_SPEED_1000, GECMR);  in ravb_set_rate()
404 	ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);  in ravb_emac_init()
407 	ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) |  in ravb_emac_init()
414 	ravb_write(ndev,  in ravb_emac_init()
417 	ravb_write(ndev,  in ravb_emac_init()
421 	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);  in ravb_emac_init()
424 	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);  in ravb_emac_init()
458 	ravb_write(ndev,  in ravb_dmac_init()
462 	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);  in ravb_dmac_init()
465 	ravb_write(ndev, TCCR_TFEN, TCCR);  in ravb_dmac_init()
470 		ravb_write(ndev, 0, DIL);  in ravb_dmac_init()
472 		ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);  in ravb_dmac_init()
475 	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);  in ravb_dmac_init()
477 	ravb_write(ndev, 0, RIC1);  in ravb_dmac_init()
479 	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);  in ravb_dmac_init()
481 	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);  in ravb_dmac_init()
700 	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */  in ravb_emac_interrupt_unlocked()
742 	ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);  in ravb_error_interrupt()
745 		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),  in ravb_error_interrupt()
774 				ravb_write(ndev, ric0 & ~BIT(q), RIC0);  in ravb_queue_interrupt()
775 				ravb_write(ndev, tic & ~BIT(q), TIC);  in ravb_queue_interrupt()
777 				ravb_write(ndev, BIT(q), RID0);  in ravb_queue_interrupt()
778 				ravb_write(ndev, BIT(q), TID);  in ravb_queue_interrupt()
799 		ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);  in ravb_timestamp_interrupt()
934 			ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);  in ravb_poll()
942 			ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);  in ravb_poll()
958 		ravb_write(ndev, mask, RIE0);  in ravb_poll()
959 		ravb_write(ndev, mask, TIE);  in ravb_poll()
1617 	ravb_write(ndev, 0, TROCR);	/* (write clear) */  in ravb_get_stats()
1619 	ravb_write(ndev, 0, CDCR);	/* (write clear) */  in ravb_get_stats()
1621 	ravb_write(ndev, 0, LCCR);	/* (write clear) */  in ravb_get_stats()
1624 	ravb_write(ndev, 0, CERCR);	/* (write clear) */  in ravb_get_stats()
1626 	ravb_write(ndev, 0, CEECR);	/* (write clear) */  in ravb_get_stats()
1670 	ravb_write(ndev, 0, RIC0);  in ravb_close()
1671 	ravb_write(ndev, 0, RIC2);  in ravb_close()
1672 	ravb_write(ndev, 0, TIC);  in ravb_close()
1934 	ravb_write(ndev, inc, GTI);  in ravb_set_gti()
2110 	ravb_write(ndev, priv->desc_bat_dma, DBAT);  in ravb_probe()
2186 	ravb_write(ndev, CCC_OPC_RESET, CCC);  in ravb_remove()
2204 	ravb_write(ndev, 0, RIC0);  in ravb_wol_setup()
2205 	ravb_write(ndev, 0, RIC2);  in ravb_wol_setup()
2206 	ravb_write(ndev, 0, TIC);  in ravb_wol_setup()
2212 	ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);  in ravb_wol_setup()
2265 		ravb_write(ndev, CCC_OPC_RESET, CCC);  in ravb_resume()
2287 	ravb_write(ndev, priv->desc_bat_dma, DBAT);  in ravb_resume()