Lines Matching refs:RTL_W32
85 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) macro
845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); in r8168_phy_ocp_write()
855 RTL_W32(tp, GPHY_OCP, reg << 15); in r8168_phy_ocp_read()
866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); in r8168_mac_ocp_write()
874 RTL_W32(tp, OCPDR, reg << 15); in r8168_mac_ocp_read()
924 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
938 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
959 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); in r8168dp_1_mdio_access()
960 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); in r8168dp_1_mdio_access()
961 RTL_W32(tp, EPHY_RXER_NUM, 0); in r8168dp_1_mdio_access()
977 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); in r8168dp_1_mdio_read()
978 RTL_W32(tp, EPHY_RXER_NUM, 0); in r8168dp_1_mdio_read()
988 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | in rtl_ephy_write()
1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); in rtl_ephy_read()
1073 RTL_W32(tp, ERIDR, val); in rtl_eri_write()
1074 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); in rtl_eri_write()
1081 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); in rtl_eri_read()
1098 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1128 RTL_W32(tp, OCPDR, data); in r8168dp_ocp_write()
1129 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1317 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); in rtl8168d_efuse_read()
1612 RTL_W32(tp, RxConfig, rx_config); in rtl8169_set_features()
1710 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); in rtl8169_do_counters()
1713 RTL_W32(tp, CounterAddrLow, cmd); in rtl8169_do_counters()
1714 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); in rtl8169_do_counters()
4090 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); in rtl_rar_set()
4093 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); in rtl_rar_set()
4168 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | in rtl_wol_suspend_quirk()
4282 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); in rtl_init_rxcfg()
4287 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); in rtl_init_rxcfg()
4290 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); in rtl_init_rxcfg()
4293 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); in rtl_init_rxcfg()
4496 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); in rtl_rx_close()
4545 RTL_W32(tp, TxConfig, val); in rtl_set_tx_config_registers()
4561 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
4562 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
4563 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
4564 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
4586 RTL_W32(tp, 0x7c, p->val); in rtl8169_set_magic_reg()
4638 RTL_W32(tp, MAR0 + 4, mc_filter[1]); in rtl_set_rx_mode()
4639 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
4641 RTL_W32(tp, RxConfig, tmp); in rtl_set_rx_mode()
4692 RTL_W32(tp, RxMissed, 0); in rtl_hw_start_8169()
4704 RTL_W32(tp, CSIDR, value); in rtl_csi_write()
4705 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | in rtl_csi_write()
4715 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | in rtl_csi_read()
5007 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); in rtl_hw_start_8168e_1()
5008 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); in rtl_hw_start_8168e_1()
5046 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168e_2()
5075 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168f()
5130 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8168g()
5232 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8168h_1()
5312 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_hw_start_8168ep()
5586 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
5589 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
5615 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
5639 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
5641 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); in rtl_hw_start_8106()
6586 RTL_W32(tp, RxMissed, 0); in rtl8169_rx_missed()
7184 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); in rtl_hw_init_8168g()