3241 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3276 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_force_linkspeed()
3278 			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_force_linkspeed()
3280 		txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_force_linkspeed()
3282 	writel(txreg, base + NvRegTxDeferral);  in nv_force_linkspeed()
3285 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_force_linkspeed()
3289 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_force_linkspeed()
3291 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_force_linkspeed()
3293 	writel(txreg, base + NvRegTxWatermark);  in nv_force_linkspeed()
3325 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3457 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_update_linkspeed()
3461 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;  in nv_update_linkspeed()
3463 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;  in nv_update_linkspeed()
3465 				txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_update_linkspeed()
3470 			txreg = NVREG_TX_DEFERRAL_MII_STRETCH;  in nv_update_linkspeed()
3472 			txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_update_linkspeed()
3474 	writel(txreg, base + NvRegTxDeferral);  in nv_update_linkspeed()
3477 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_update_linkspeed()
3480 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_update_linkspeed()
3482 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_update_linkspeed()
3484 	writel(txreg, base + NvRegTxWatermark);  in nv_update_linkspeed()
5644 	u32 powerstate, txreg;  in nv_probe()  local
5816 	txreg = readl(base + NvRegTransmitPoll);  in nv_probe()
5825 	} else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {  in nv_probe()
5849 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);  in nv_probe()