3241 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3251 		phyreg = readl(base + NvRegSlotTime);  in nv_force_linkspeed()
3252 		phyreg &= ~(0x3FF00);  in nv_force_linkspeed()
3254 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3256 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3258 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_force_linkspeed()
3259 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3262 	phyreg = readl(base + NvRegPhyInterface);  in nv_force_linkspeed()
3263 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_force_linkspeed()
3265 		phyreg |= PHY_HALF;  in nv_force_linkspeed()
3267 		phyreg |= PHY_100;  in nv_force_linkspeed()
3270 		phyreg |= PHY_1000;  in nv_force_linkspeed()
3271 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3273 	if (phyreg & PHY_RGMII) {  in nv_force_linkspeed()
3325 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3434 		phyreg = readl(base + NvRegSlotTime);  in nv_update_linkspeed()
3435 		phyreg &= ~(0x3FF00);  in nv_update_linkspeed()
3438 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_update_linkspeed()
3440 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_update_linkspeed()
3441 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3444 	phyreg = readl(base + NvRegPhyInterface);  in nv_update_linkspeed()
3445 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_update_linkspeed()
3447 		phyreg |= PHY_HALF;  in nv_update_linkspeed()
3449 		phyreg |= PHY_100;  in nv_update_linkspeed()
3451 		phyreg |= PHY_1000;  in nv_update_linkspeed()
3452 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3455 	if (phyreg & PHY_RGMII) {  in nv_update_linkspeed()