Lines Matching refs:phyaddr
765 int phyaddr; member
1189 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1198 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1223 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1245 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1247 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1249 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1252 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1255 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1258 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1270 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1273 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1286 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1289 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1293 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1296 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1310 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1313 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1315 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1317 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1320 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1322 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1332 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1335 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1338 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1342 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1346 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1348 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1351 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1354 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1358 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1360 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1362 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1364 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1367 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1370 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1374 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1378 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1380 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1383 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1399 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1401 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1432 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1436 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1446 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1449 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1457 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1465 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1473 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1522 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1525 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1529 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
3248 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3332 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3345 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3346 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3381 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3382 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3386 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3387 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3454 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4312 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4322 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4334 cmd->base.phy_address = np->phyaddr; in nv_get_link_ksettings()
4358 if (cmd->base.phy_address != np->phyaddr) { in nv_set_link_ksettings()
4417 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4431 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4434 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4438 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4443 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4454 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4461 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4480 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4484 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4486 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4489 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4502 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4563 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4573 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4769 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4775 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4779 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4781 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4810 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4820 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
4964 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
4965 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5394 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5395 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5480 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5593 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5594 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
5973 int phyaddr = i & 0x1F; in nv_probe() local
5976 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
5981 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
5989 np->phyaddr = phyaddr; in nv_probe()
5997 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6011 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6041 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6088 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6089 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6092 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6093 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6096 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6098 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()