1267 	u32 phy_reserved;  in init_realtek_8201()  local
1270 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201()
1272 		phy_reserved |= PHY_REALTEK_INIT7;  in init_realtek_8201()
1274 			   PHY_REALTEK_INIT_REG6, phy_reserved))  in init_realtek_8201()
1283 	u32 phy_reserved;  in init_realtek_8201_cross()  local
1289 		phy_reserved = mii_rw(dev, np->phyaddr,  in init_realtek_8201_cross()
1291 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in init_realtek_8201_cross()
1292 		phy_reserved |= PHY_REALTEK_INIT3;  in init_realtek_8201_cross()
1294 			   PHY_REALTEK_INIT_REG2, phy_reserved))  in init_realtek_8201_cross()
1307 	u32 phy_reserved;  in init_cicada()  local
1310 		phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);  in init_cicada()
1311 		phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);  in init_cicada()
1312 		phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);  in init_cicada()
1313 		if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))  in init_cicada()
1315 		phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);  in init_cicada()
1316 		phy_reserved |= PHY_CICADA_INIT5;  in init_cicada()
1317 		if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))  in init_cicada()
1320 	phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);  in init_cicada()
1321 	phy_reserved |= PHY_CICADA_INIT6;  in init_cicada()
1322 	if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))  in init_cicada()
1330 	u32 phy_reserved;  in init_vitesse()  local
1338 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1340 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1342 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1344 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1345 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1346 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1354 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1356 	phy_reserved &= ~PHY_VITESSE_INIT_MSK1;  in init_vitesse()
1357 	phy_reserved |= PHY_VITESSE_INIT3;  in init_vitesse()
1358 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1360 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1362 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
1370 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1372 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))  in init_vitesse()
1374 	phy_reserved = mii_rw(dev, np->phyaddr,  in init_vitesse()
1376 	phy_reserved &= ~PHY_VITESSE_INIT_MSK2;  in init_vitesse()
1377 	phy_reserved |= PHY_VITESSE_INIT8;  in init_vitesse()
1378 	if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))  in init_vitesse()
6083 	u16 phy_reserved, mii_control;  in nv_restore_phy()  local
6089 		phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);  in nv_restore_phy()
6090 		phy_reserved &= ~PHY_REALTEK_INIT_MSK1;  in nv_restore_phy()
6091 		phy_reserved |= PHY_REALTEK_INIT8;  in nv_restore_phy()
6092 		mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);  in nv_restore_phy()