236 	NvRegTxRxControl = 0x144,  enumerator
1629 	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_txrx_reset()
1632 	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_txrx_reset()
1642 	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_mac_reset()
1662 	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_mac_reset()
2342 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_start_xmit()
2527 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_start_xmit_optimized()
2545 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_tx_flip_ownership()
3072 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_change_mtu()
4154 			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_do_nic_poll()
4707 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_set_ringparam()
4883 	writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_vlan_mode()
4910 			writel(np->txrxctl_bits, base + NvRegTxRxControl);  in nv_set_features()
5132 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_loopback_test()
5260 			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_self_test()
5436 	writel(np->txrxctl_bits, base + NvRegTxRxControl);  in nv_open()
5439 	writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);  in nv_open()