298 		&channel->common_reg->set_msix_mask_vect[msix_id%4]);  in vxge_hw_channel_msix_mask()
316 		&channel->common_reg->clear_msix_mask_vect[msix_id%4]);  in vxge_hw_channel_msix_unmask()
333 		&channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);  in vxge_hw_channel_msix_clear()
388 			writeq(val64, &hldev->common_reg->tim_int_status0);  in vxge_hw_device_intr_enable()
390 			writeq(~val64, &hldev->common_reg->tim_int_mask0);  in vxge_hw_device_intr_enable()
398 					&hldev->common_reg->tim_int_status1);  in vxge_hw_device_intr_enable()
401 					&hldev->common_reg->tim_int_mask1);  in vxge_hw_device_intr_enable()
405 	val64 = readq(&hldev->common_reg->titan_general_int_status);  in vxge_hw_device_intr_enable()
427 	writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);  in vxge_hw_device_intr_disable()
429 		&hldev->common_reg->tim_int_mask1);  in vxge_hw_device_intr_disable()
457 				&hldev->common_reg->titan_mask_all_int);  in vxge_hw_device_mask_all()
476 			&hldev->common_reg->titan_mask_all_int);  in vxge_hw_device_unmask_all()
491 	val32 = readl(&hldev->common_reg->titan_general_int_status);  in vxge_hw_device_flush_io()
899 	val64 = readq(&hldev->common_reg->titan_general_int_status);  in vxge_hw_device_begin_irq()
910 		adapter_status = readq(&hldev->common_reg->adapter_status);  in vxge_hw_device_begin_irq()
983 				&hldev->common_reg->tim_int_status0);  in vxge_hw_device_clear_tx_rx()
991 				&hldev->common_reg->tim_int_status1);  in vxge_hw_device_clear_tx_rx()
2245 		&hldev->common_reg->set_msix_mask_vect[msix_id % 4]);  in vxge_hw_vpath_msix_mask()
2267 			&hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);  in vxge_hw_vpath_msix_clear()
2271 			&hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);  in vxge_hw_vpath_msix_clear()
2292 			&hldev->common_reg->clear_msix_mask_vect[msix_id%4]);  in vxge_hw_vpath_msix_unmask()
2313 	val64 = readq(&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_mask_tx_rx()
2319 			&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_mask_tx_rx()
2322 	val64 = readl(&hldev->common_reg->tim_int_mask1);  in vxge_hw_vpath_inta_mask_tx_rx()
2329 			&hldev->common_reg->tim_int_mask1);  in vxge_hw_vpath_inta_mask_tx_rx()
2351 	val64 = readq(&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_unmask_tx_rx()
2357 			&hldev->common_reg->tim_int_mask0);  in vxge_hw_vpath_inta_unmask_tx_rx()
2365 			&hldev->common_reg->tim_int_mask1);  in vxge_hw_vpath_inta_unmask_tx_rx()
2417 			  readl(&ring->common_reg->titan_general_int_status);  in vxge_hw_vpath_poll_rx()