33 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)  in vxge_hw_vpath_set_zero_rx_frm_len()  argument
37 	val64 = readq(&vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
39 	writeq(val64, &vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
40 	val64 = readq(&vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_set_zero_rx_frm_len()
48 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in vxge_hw_vpath_wait_receive_idle()  local
54 	vp_reg = vpath->vp_reg;  in vxge_hw_vpath_wait_receive_idle()
56 	vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);  in vxge_hw_vpath_wait_receive_idle()
63 	val64 = readq(&vp_reg->prc_cfg6);  in vxge_hw_vpath_wait_receive_idle()
73 		rxd_count = readq(&vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_wait_receive_idle()
78 		val64 = readq(&vp_reg->frm_in_progress_cnt);  in vxge_hw_vpath_wait_receive_idle()
160 	struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;  in vxge_hw_vpath_fw_api()  local
171 	writeq(*data0, &vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
172 	writeq(*data1, &vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
182 					   &vp_reg->rts_access_steer_ctrl,  in vxge_hw_vpath_fw_api()
198 					&vp_reg->rts_access_steer_ctrl,  in vxge_hw_vpath_fw_api()
206 	val64 = readq(&vp_reg->rts_access_steer_ctrl);  in vxge_hw_vpath_fw_api()
208 		*data0 = readq(&vp_reg->rts_access_steer_data0);  in vxge_hw_vpath_fw_api()
209 		*data1 = readq(&vp_reg->rts_access_steer_data1);  in vxge_hw_vpath_fw_api()
740 		hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];  in __vxge_hw_device_host_info_get()
1054 		vpath.vp_reg = bar0 + val64;  in vxge_hw_device_hw_info_get()
1077 		vpath.vp_reg = bar0 + val64;  in vxge_hw_device_hw_info_get()
1413 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_stats_access()  local
1420 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_stats_access()
1427 				&vp_reg->xmac_stats_access_cmd,  in __vxge_hw_vpath_stats_access()
1431 		*stat = readq(&vp_reg->xmac_stats_access_data);  in __vxge_hw_vpath_stats_access()
1511 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_stats_get()  local
1517 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_stats_get()
1519 	val64 = readq(&vp_reg->vpath_debug_stats0);  in __vxge_hw_vpath_stats_get()
1523 	val64 = readq(&vp_reg->vpath_debug_stats1);  in __vxge_hw_vpath_stats_get()
1527 	val64 = readq(&vp_reg->vpath_debug_stats2);  in __vxge_hw_vpath_stats_get()
1531 	val64 = readq(&vp_reg->vpath_debug_stats3);  in __vxge_hw_vpath_stats_get()
1535 	val64 = readq(&vp_reg->vpath_debug_stats4);  in __vxge_hw_vpath_stats_get()
1539 	val64 = readq(&vp_reg->vpath_debug_stats5);  in __vxge_hw_vpath_stats_get()
1543 	val64 = readq(&vp_reg->vpath_debug_stats6);  in __vxge_hw_vpath_stats_get()
1547 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1552 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1557 	val64 = readq(&vp_reg->vpath_genstats_count23);  in __vxge_hw_vpath_stats_get()
1562 	val64 = readq(&vp_reg->vpath_genstats_count01);  in __vxge_hw_vpath_stats_get()
1567 	val64 = readq(&vp_reg->vpath_genstats_count4);  in __vxge_hw_vpath_stats_get()
1572 	val64 = readq(&vp_reg->vpath_genstats_count5);  in __vxge_hw_vpath_stats_get()
1603 	val64 = readq(&vp_reg->rx_multi_cast_stats);  in __vxge_hw_vpath_stats_get()
1607 	val64 = readq(&vp_reg->rx_frm_transferred);  in __vxge_hw_vpath_stats_get()
1611 	val64 = readq(&vp_reg->rxd_returned);  in __vxge_hw_vpath_stats_get()
1615 	val64 = readq(&vp_reg->dbg_stats_rx_mpa);  in __vxge_hw_vpath_stats_get()
1623 	val64 = readq(&vp_reg->dbg_stats_rx_fau);  in __vxge_hw_vpath_stats_get()
1631 	val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);  in __vxge_hw_vpath_stats_get()
2829 	ring->vp_reg = vp->vpath->vp_reg;  in __vxge_hw_ring_create()
3473 	fifo->vp_reg = vpath->vp_reg;  in __vxge_hw_fifo_create()
3568 	struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_pci_read()  local
3575 	writeq(val64, &vp_reg->pci_config_access_cfg1);  in __vxge_hw_vpath_pci_read()
3578 			&vp_reg->pci_config_access_cfg2);  in __vxge_hw_vpath_pci_read()
3582 			&vp_reg->pci_config_access_cfg2,  in __vxge_hw_vpath_pci_read()
3588 	val64 = readq(&vp_reg->pci_config_access_status);  in __vxge_hw_vpath_pci_read()
3945 	rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_check_leak()
3946 	rxd_spat = readq(&ring->vp_reg->prc_cfg6);  in vxge_hw_vpath_check_leak()
4069 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_prc_configure()  local
4072 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_prc_configure()
4078 	val64 = readq(&vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4080 	writeq(val64, &vp_reg->prc_cfg1);  in __vxge_hw_vpath_prc_configure()
4082 	val64 = readq(&vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4084 	writeq(val64, &vpath->vp_reg->prc_cfg6);  in __vxge_hw_vpath_prc_configure()
4086 	val64 = readq(&vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4109 	writeq(val64, &vp_reg->prc_cfg7);  in __vxge_hw_vpath_prc_configure()
4113 					vpath->ringh) >> 3), &vp_reg->prc_cfg5);  in __vxge_hw_vpath_prc_configure()
4115 	val64 = readq(&vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4127 	writeq(val64, &vp_reg->prc_cfg4);  in __vxge_hw_vpath_prc_configure()
4142 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_kdfc_configure()  local
4145 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_kdfc_configure()
4146 	status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);  in __vxge_hw_vpath_kdfc_configure()
4151 	val64 = readq(&vp_reg->kdfc_drbl_triplet_total);  in __vxge_hw_vpath_kdfc_configure()
4173 	writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);  in __vxge_hw_vpath_kdfc_configure()
4176 		&vp_reg->kdfc_fifo_trpl_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4178 	val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4190 	writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);  in __vxge_hw_vpath_kdfc_configure()
4191 	writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);  in __vxge_hw_vpath_kdfc_configure()
4214 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_mac_configure()  local
4217 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_mac_configure()
4221 			vpath->vsport_number), &vp_reg->xmac_vsport_choice);  in __vxge_hw_vpath_mac_configure()
4225 		val64 = readq(&vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4235 		writeq(val64, &vp_reg->xmac_rpa_vcfg);  in __vxge_hw_vpath_mac_configure()
4236 		val64 = readq(&vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4251 		writeq(val64, &vp_reg->rxmac_vcfg0);  in __vxge_hw_vpath_mac_configure()
4253 		val64 = readq(&vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4265 		writeq(val64, &vp_reg->rxmac_vcfg1);  in __vxge_hw_vpath_mac_configure()
4280 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_tim_configure()  local
4284 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_tim_configure()
4287 	writeq(0, &vp_reg->tim_dest_addr);  in __vxge_hw_vpath_tim_configure()
4288 	writeq(0, &vp_reg->tim_vpath_map);  in __vxge_hw_vpath_tim_configure()
4289 	writeq(0, &vp_reg->tim_bitmap);  in __vxge_hw_vpath_tim_configure()
4290 	writeq(0, &vp_reg->tim_remap);  in __vxge_hw_vpath_tim_configure()
4295 			VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);  in __vxge_hw_vpath_tim_configure()
4297 	val64 = readq(&vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4299 	writeq(val64, &vp_reg->tim_pci_cfg);  in __vxge_hw_vpath_tim_configure()
4303 		val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4346 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4349 		val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4375 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4376 		val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4404 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);  in __vxge_hw_vpath_tim_configure()
4410 		val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4453 		writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4456 		val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4482 		writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4483 		val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4511 		writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);  in __vxge_hw_vpath_tim_configure()
4516 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4517 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4518 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);  in __vxge_hw_vpath_tim_configure()
4519 	writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4520 	writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4521 	writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);  in __vxge_hw_vpath_tim_configure()
4526 	writeq(val64, &vp_reg->tim_wrkld_clc);  in __vxge_hw_vpath_tim_configure()
4543 	struct vxge_hw_vpath_reg __iomem *vp_reg;  in __vxge_hw_vpath_initialize()  local
4551 	vp_reg = vpath->vp_reg;  in __vxge_hw_vpath_initialize()
4553 	status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);  in __vxge_hw_vpath_initialize()
4569 	val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4589 	writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);  in __vxge_hw_vpath_initialize()
4661 	vpath->vp_reg = hldev->vpath_reg[vp_id];  in __vxge_hw_vp_initialize()
4715 	val64 = readq(&vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4720 	writeq(val64, &vpath->vp_reg->rxmac_vcfg0);  in vxge_hw_vpath_mtu_set()
4858 	writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_open()
4906 		new_count = readq(&vpath->vp_reg->rxdmem_size);  in vxge_hw_vpath_rx_doorbell_init()
4914 		&vpath->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_rx_doorbell_init()
4915 	readl(&vpath->vp_reg->prc_rxd_doorbell);  in vxge_hw_vpath_rx_doorbell_init()
4918 	val64 = readq(&vpath->vp_reg->prc_cfg6);  in vxge_hw_vpath_rx_doorbell_init()
5076 		&vpath->vp_reg->stats_cfg);  in vxge_hw_vpath_recover_from_reset()