208 	if (addr >= EIE && addr <= ECON1)  in enc28j60_set_bank()
214 			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,  in enc28j60_set_bank()
217 			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,  in enc28j60_set_bank()
222 			spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,  in enc28j60_set_bank()
225 			spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,  in enc28j60_set_bank()
557 		nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),  in enc28j60_dump_regs()
644 		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);  in enc28j60_lowpower()
646 		poll_ready(priv, ECON1, ECON1_TXRTS, 0);  in enc28j60_lowpower()
669 	spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);  in enc28j60_hw_init()
767 	nolock_reg_bfset(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_enable()
777 	nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_disable()
923 		nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_rx()
924 		nolock_reg_bfset(priv, ECON1, ECON1_RXRST);  in enc28j60_hw_rx()
925 		nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);  in enc28j60_hw_rx()
928 		nolock_reg_bfset(priv, ECON1, ECON1_RXEN);  in enc28j60_hw_rx()
1086 	locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);  in enc28j60_tx_clear()
1184 			locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);  in enc28j60_irq_work_handler()
1190 			nolock_reg_bfset(priv, ECON1, ECON1_TXRST);  in enc28j60_irq_work_handler()
1191 			nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);  in enc28j60_irq_work_handler()
1201 					locked_reg_bfset(priv, ECON1,  in enc28j60_irq_work_handler()
1282 	locked_reg_bfset(priv, ECON1, ECON1_TXRTS);  in enc28j60_hw_tx()