Lines Matching refs:pmlp_pl
641 char pmlp_pl[MLXSW_REG_PMLP_LEN]; in mlxsw_sp_port_module_info_get() local
644 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); in mlxsw_sp_port_module_info_get()
645 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); in mlxsw_sp_port_module_info_get()
648 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); in mlxsw_sp_port_module_info_get()
649 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); in mlxsw_sp_port_module_info_get()
650 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); in mlxsw_sp_port_module_info_get()
658 char pmlp_pl[MLXSW_REG_PMLP_LEN]; in mlxsw_sp_port_module_map() local
661 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); in mlxsw_sp_port_module_map()
662 mlxsw_reg_pmlp_width_set(pmlp_pl, width); in mlxsw_sp_port_module_map()
664 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); in mlxsw_sp_port_module_map()
665 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ in mlxsw_sp_port_module_map()
668 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); in mlxsw_sp_port_module_map()
674 char pmlp_pl[MLXSW_REG_PMLP_LEN]; in mlxsw_sp_port_module_unmap() local
676 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); in mlxsw_sp_port_module_unmap()
677 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); in mlxsw_sp_port_module_unmap()
678 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); in mlxsw_sp_port_module_unmap()