724 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)  in mlx4_QUERY_DEV_CAP()  argument
830 	dev_cap->flags2 = 0;  in mlx4_QUERY_DEV_CAP()
844 	dev_cap->reserved_qps = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
846 	dev_cap->max_qps = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
848 	dev_cap->reserved_srqs = 1 << (field >> 4);  in mlx4_QUERY_DEV_CAP()
850 	dev_cap->max_srqs = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
852 	dev_cap->max_cq_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
854 	dev_cap->reserved_cqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
856 	dev_cap->max_cqs = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
858 	dev_cap->max_mpts = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
860 	dev_cap->reserved_eqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
862 	dev_cap->max_eqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
864 	dev_cap->reserved_mtts = 1 << (field >> 4);  in mlx4_QUERY_DEV_CAP()
866 	dev_cap->reserved_mrws = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
868 	dev_cap->num_sys_eqs = size & 0xfff;  in mlx4_QUERY_DEV_CAP()
870 	dev_cap->max_requester_per_qp = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
872 	dev_cap->max_responder_per_qp = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
876 		dev_cap->max_gso_sz = 0;  in mlx4_QUERY_DEV_CAP()
878 		dev_cap->max_gso_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
882 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;  in mlx4_QUERY_DEV_CAP()
884 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;  in mlx4_QUERY_DEV_CAP()
887 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;  in mlx4_QUERY_DEV_CAP()
888 		dev_cap->max_rss_tbl_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
890 		dev_cap->max_rss_tbl_sz = 0;  in mlx4_QUERY_DEV_CAP()
892 	dev_cap->max_rdma_global = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
894 	dev_cap->local_ca_ack_delay = field & 0x1f;  in mlx4_QUERY_DEV_CAP()
896 	dev_cap->num_ports = field & 0xf;  in mlx4_QUERY_DEV_CAP()
898 	dev_cap->max_msg_sz = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
901 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;  in mlx4_QUERY_DEV_CAP()
904 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;  in mlx4_QUERY_DEV_CAP()
905 	dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;  in mlx4_QUERY_DEV_CAP()
907 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;  in mlx4_QUERY_DEV_CAP()
910 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;  in mlx4_QUERY_DEV_CAP()
913 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;  in mlx4_QUERY_DEV_CAP()
915 	dev_cap->fs_max_num_qp_per_entry = field;  in mlx4_QUERY_DEV_CAP()
918 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT;  in mlx4_QUERY_DEV_CAP()
921 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;  in mlx4_QUERY_DEV_CAP()
923 	dev_cap->stat_rate_support = stat_rate;  in mlx4_QUERY_DEV_CAP()
926 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;  in mlx4_QUERY_DEV_CAP()
929 	dev_cap->flags = flags | (u64)ext_flags << 32;  in mlx4_QUERY_DEV_CAP()
931 	dev_cap->wol_port[1] = !!(field & 0x20);  in mlx4_QUERY_DEV_CAP()
932 	dev_cap->wol_port[2] = !!(field & 0x40);  in mlx4_QUERY_DEV_CAP()
934 	dev_cap->reserved_uars = field >> 4;  in mlx4_QUERY_DEV_CAP()
936 	dev_cap->uar_size = 1 << ((field & 0x3f) + 20);  in mlx4_QUERY_DEV_CAP()
938 	dev_cap->min_page_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
943 		dev_cap->bf_reg_size = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
945 		if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))  in mlx4_QUERY_DEV_CAP()
947 		dev_cap->bf_regs_per_page = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
949 		dev_cap->bf_reg_size = 0;  in mlx4_QUERY_DEV_CAP()
953 	dev_cap->max_sq_sg = field;  in mlx4_QUERY_DEV_CAP()
955 	dev_cap->max_sq_desc_sz = size;  in mlx4_QUERY_DEV_CAP()
959 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_USER_MAC_EN;  in mlx4_QUERY_DEV_CAP()
962 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP;  in mlx4_QUERY_DEV_CAP()
964 	dev_cap->max_qp_per_mcg = 1 << field;  in mlx4_QUERY_DEV_CAP()
966 	dev_cap->reserved_mgms = field & 0xf;  in mlx4_QUERY_DEV_CAP()
968 	dev_cap->max_mcgs = 1 << field;  in mlx4_QUERY_DEV_CAP()
970 	dev_cap->reserved_pds = field >> 4;  in mlx4_QUERY_DEV_CAP()
972 	dev_cap->max_pds = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
974 	dev_cap->reserved_xrcds = field >> 4;  in mlx4_QUERY_DEV_CAP()
976 	dev_cap->max_xrcds = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
979 	dev_cap->rdmarc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
981 	dev_cap->qpc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
983 	dev_cap->aux_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
985 	dev_cap->altc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
987 	dev_cap->eqc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
989 	dev_cap->cqc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
991 	dev_cap->srq_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
993 	dev_cap->cmpt_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
995 	dev_cap->mtt_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
997 	dev_cap->dmpt_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
1000 	dev_cap->max_srq_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
1002 	dev_cap->max_qp_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
1004 	dev_cap->resize_srq = field & 1;  in mlx4_QUERY_DEV_CAP()
1006 	dev_cap->max_rq_sg = field;  in mlx4_QUERY_DEV_CAP()
1008 	dev_cap->max_rq_desc_sz = size;  in mlx4_QUERY_DEV_CAP()
1011 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;  in mlx4_QUERY_DEV_CAP()
1013 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;  in mlx4_QUERY_DEV_CAP()
1015 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
1017 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
1018 	MLX4_GET(dev_cap->bmme_flags, outbox,  in mlx4_QUERY_DEV_CAP()
1020 	if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)  in mlx4_QUERY_DEV_CAP()
1021 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;  in mlx4_QUERY_DEV_CAP()
1022 	if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)  in mlx4_QUERY_DEV_CAP()
1023 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;  in mlx4_QUERY_DEV_CAP()
1026 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;  in mlx4_QUERY_DEV_CAP()
1028 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;  in mlx4_QUERY_DEV_CAP()
1031 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;  in mlx4_QUERY_DEV_CAP()
1033 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;  in mlx4_QUERY_DEV_CAP()
1035 	MLX4_GET(dev_cap->reserved_lkey, outbox,  in mlx4_QUERY_DEV_CAP()
1039 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;  in mlx4_QUERY_DEV_CAP()
1041 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;  in mlx4_QUERY_DEV_CAP()
1043 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW;  in mlx4_QUERY_DEV_CAP()
1046 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;  in mlx4_QUERY_DEV_CAP()
1049 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;  in mlx4_QUERY_DEV_CAP()
1052 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;  in mlx4_QUERY_DEV_CAP()
1054 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;  in mlx4_QUERY_DEV_CAP()
1055 	MLX4_GET(dev_cap->max_icm_sz, outbox,  in mlx4_QUERY_DEV_CAP()
1057 	if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)  in mlx4_QUERY_DEV_CAP()
1058 		MLX4_GET(dev_cap->max_counters, outbox,  in mlx4_QUERY_DEV_CAP()
1064 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;  in mlx4_QUERY_DEV_CAP()
1066 	MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,  in mlx4_QUERY_DEV_CAP()
1068 	dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;  in mlx4_QUERY_DEV_CAP()
1069 	MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,  in mlx4_QUERY_DEV_CAP()
1071 	dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;  in mlx4_QUERY_DEV_CAP()
1074 	dev_cap->rl_caps.num_rates = size;  in mlx4_QUERY_DEV_CAP()
1075 	if (dev_cap->rl_caps.num_rates) {  in mlx4_QUERY_DEV_CAP()
1076 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;  in mlx4_QUERY_DEV_CAP()
1078 		dev_cap->rl_caps.max_val  = size & 0xfff;  in mlx4_QUERY_DEV_CAP()
1079 		dev_cap->rl_caps.max_unit = size >> 14;  in mlx4_QUERY_DEV_CAP()
1081 		dev_cap->rl_caps.min_val  = size & 0xfff;  in mlx4_QUERY_DEV_CAP()
1082 		dev_cap->rl_caps.min_unit = size >> 14;  in mlx4_QUERY_DEV_CAP()
1085 	MLX4_GET(dev_cap->health_buffer_addrs, outbox,  in mlx4_QUERY_DEV_CAP()
1090 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;  in mlx4_QUERY_DEV_CAP()
1092 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;  in mlx4_QUERY_DEV_CAP()
1094 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;  in mlx4_QUERY_DEV_CAP()
1096 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;  in mlx4_QUERY_DEV_CAP()
1098 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;  in mlx4_QUERY_DEV_CAP()
1100 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;  in mlx4_QUERY_DEV_CAP()
1102 	for (i = 1; i <= dev_cap->num_ports; i++) {  in mlx4_QUERY_DEV_CAP()
1103 		err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);  in mlx4_QUERY_DEV_CAP()
1113 	if (dev_cap->num_sys_eqs == 0)  in mlx4_QUERY_DEV_CAP()
1114 		dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,  in mlx4_QUERY_DEV_CAP()
1115 					    dev_cap->reserved_eqs);  in mlx4_QUERY_DEV_CAP()
1117 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;  in mlx4_QUERY_DEV_CAP()
1124 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)  in mlx4_dev_cap_dump()  argument
1126 	if (dev_cap->bf_reg_size > 0)  in mlx4_dev_cap_dump()
1128 			 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);  in mlx4_dev_cap_dump()
1133 		 dev_cap->bmme_flags, dev_cap->reserved_lkey);  in mlx4_dev_cap_dump()
1135 		 (unsigned long long) dev_cap->max_icm_sz >> 20);  in mlx4_dev_cap_dump()
1137 		 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);  in mlx4_dev_cap_dump()
1139 		 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);  in mlx4_dev_cap_dump()
1141 		 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);  in mlx4_dev_cap_dump()
1143 		 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,  in mlx4_dev_cap_dump()
1144 		 dev_cap->eqc_entry_sz);  in mlx4_dev_cap_dump()
1146 		 dev_cap->reserved_mrws, dev_cap->reserved_mtts);  in mlx4_dev_cap_dump()
1148 		 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);  in mlx4_dev_cap_dump()
1150 		 dev_cap->max_pds, dev_cap->reserved_mgms);  in mlx4_dev_cap_dump()
1152 		 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);  in mlx4_dev_cap_dump()
1154 		 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,  in mlx4_dev_cap_dump()
1155 		 dev_cap->port_cap[1].max_port_width);  in mlx4_dev_cap_dump()
1157 		 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);  in mlx4_dev_cap_dump()
1159 		 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);  in mlx4_dev_cap_dump()
1160 	mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);  in mlx4_dev_cap_dump()
1161 	mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);  in mlx4_dev_cap_dump()
1162 	mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);  in mlx4_dev_cap_dump()
1164 		 dev_cap->dmfs_high_rate_qpn_base);  in mlx4_dev_cap_dump()
1166 		 dev_cap->dmfs_high_rate_qpn_range);  in mlx4_dev_cap_dump()
1168 	if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {  in mlx4_dev_cap_dump()
1169 		struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;  in mlx4_dev_cap_dump()
1176 	dump_dev_cap_flags(dev, dev_cap->flags);  in mlx4_dev_cap_dump()
1177 	dump_dev_cap_flags2(dev, dev_cap->flags2);  in mlx4_dev_cap_dump()