88 	priv->prs_shadow[index].valid = true;  in mvpp2_prs_shadow_set()
89 	priv->prs_shadow[index].lu = lu;  in mvpp2_prs_shadow_set()
96 	priv->prs_shadow[index].ri_mask = ri_mask;  in mvpp2_prs_shadow_ri_set()
97 	priv->prs_shadow[index].ri = ri;  in mvpp2_prs_shadow_ri_set()
372 		if (!priv->prs_shadow[tid].valid ||  in mvpp2_prs_flow_find()
373 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)  in mvpp2_prs_flow_find()
400 		if (!priv->prs_shadow[tid].valid)  in mvpp2_prs_tcam_first_free()
412 	if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {  in mvpp2_prs_mac_drop_all_set()
461 	if (priv->prs_shadow[tid].valid) {  in mvpp2_prs_mac_promisc_set()
510 	if (priv->prs_shadow[tid].valid) {  in mvpp2_prs_dsa_tag_set()
581 	if (priv->prs_shadow[tid].valid) {  in mvpp2_prs_dsa_tag_ethertype_set()
642 		if (!priv->prs_shadow[tid].valid ||  in mvpp2_prs_vlan_find()
643 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)  in mvpp2_prs_vlan_find()
695 			if (!priv->prs_shadow[tid_aux].valid ||  in mvpp2_prs_vlan_add()
696 			    priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)  in mvpp2_prs_vlan_add()
769 		if (!priv->prs_shadow[tid].valid ||  in mvpp2_prs_double_vlan_find()
770 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VLAN)  in mvpp2_prs_double_vlan_find()
818 			if (!priv->prs_shadow[tid_aux].valid ||  in mvpp2_prs_double_vlan_add()
819 			    priv->prs_shadow[tid_aux].lu != MVPP2_PRS_LU_VLAN)  in mvpp2_prs_double_vlan_add()
1305 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1306 	priv->prs_shadow[pe.index].finish = false;  in mvpp2_prs_etype_init()
1335 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1336 	priv->prs_shadow[pe.index].finish = true;  in mvpp2_prs_etype_init()
1367 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1368 	priv->prs_shadow[pe.index].finish = true;  in mvpp2_prs_etype_init()
1404 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1405 	priv->prs_shadow[pe.index].finish = false;  in mvpp2_prs_etype_init()
1430 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1431 	priv->prs_shadow[pe.index].finish = false;  in mvpp2_prs_etype_init()
1461 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1462 	priv->prs_shadow[pe.index].finish = false;  in mvpp2_prs_etype_init()
1487 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;  in mvpp2_prs_etype_init()
1488 	priv->prs_shadow[pe.index].finish = true;  in mvpp2_prs_etype_init()
1919 		if (!priv->prs_shadow[tid].valid ||  in mvpp2_prs_vid_range_find()
1920 		    priv->prs_shadow[tid].lu != MVPP2_PRS_LU_VID)  in mvpp2_prs_vid_range_find()
2018 	priv->prs_shadow[tid].valid = false;  in mvpp2_prs_vid_entry_remove()
2029 		if (priv->prs_shadow[tid].valid)  in mvpp2_prs_vid_remove_all()
2043 	priv->prs_shadow[tid].valid = false;  in mvpp2_prs_vid_disable_filtering()
2054 	if (priv->prs_shadow[tid].valid)  in mvpp2_prs_vid_enable_filtering()
2116 	priv->prs_shadow = devm_kcalloc(&pdev->dev, MVPP2_PRS_TCAM_SRAM_SIZE,  in mvpp2_prs_default_init()
2117 					sizeof(*priv->prs_shadow),  in mvpp2_prs_default_init()
2119 	if (!priv->prs_shadow)  in mvpp2_prs_default_init()
2192 		if (!priv->prs_shadow[tid].valid ||  in mvpp2_prs_mac_da_range_find()
2193 		    (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||  in mvpp2_prs_mac_da_range_find()
2194 		    (priv->prs_shadow[tid].udf != udf_type))  in mvpp2_prs_mac_da_range_find()
2256 		priv->prs_shadow[pe.index].valid = false;  in mvpp2_prs_mac_da_accept()
2290 	priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF;  in mvpp2_prs_mac_da_accept()
2329 		if (!priv->prs_shadow[tid].valid ||  in mvpp2_prs_mac_del_all()
2330 		    (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||  in mvpp2_prs_mac_del_all()
2331 		    (priv->prs_shadow[tid].udf != MVPP2_PRS_UDF_MAC_DEF))  in mvpp2_prs_mac_del_all()