Lines Matching refs:pe
22 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
26 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
30 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
33 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
35 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]); in mvpp2_prs_hw_write()
38 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
40 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
46 int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe, in mvpp2_prs_init_from_hw() argument
54 memset(pe, 0, sizeof(*pe)); in mvpp2_prs_init_from_hw()
55 pe->index = tid; in mvpp2_prs_init_from_hw()
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
60 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_init_from_hw()
62 if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_init_from_hw()
66 pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
101 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
103 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
104 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
105 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
106 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
110 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
114 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
116 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
120 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
123 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
124 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
125 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
129 unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
131 return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
135 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
141 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos); in mvpp2_prs_tcam_data_byte_set()
142 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos); in mvpp2_prs_tcam_data_byte_set()
143 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos; in mvpp2_prs_tcam_data_byte_set()
144 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos); in mvpp2_prs_tcam_data_byte_set()
148 void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
154 *byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff; in mvpp2_prs_tcam_data_byte_get()
155 *enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff; in mvpp2_prs_tcam_data_byte_get()
159 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
164 tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff; in mvpp2_prs_tcam_data_cmp()
169 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
179 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i); in mvpp2_prs_tcam_ai_update()
181 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i); in mvpp2_prs_tcam_ai_update()
184 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable); in mvpp2_prs_tcam_ai_update()
188 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
190 return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK; in mvpp2_prs_tcam_ai_get()
194 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
197 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
198 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
202 static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_vid() argument
205 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf); in mvpp2_prs_match_vid()
206 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff); in mvpp2_prs_match_vid()
210 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
213 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_set()
217 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
220 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_clear()
224 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
234 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i, in mvpp2_prs_sram_ri_update()
237 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ri_update()
241 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
246 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
248 return pe->sram[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
252 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
262 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i, in mvpp2_prs_sram_ai_update()
265 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ai_update()
269 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
274 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
281 bits = (pe->sram[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
282 (pe->sram[ai_off + 1] << (32 - ai_shift)); in mvpp2_prs_sram_ai_get()
290 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
295 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
297 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
303 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
308 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
311 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
315 pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] = shift & MVPP2_PRS_SRAM_SHIFT_MASK; in mvpp2_prs_sram_shift_set()
318 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
320 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
323 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
329 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
335 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
338 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
342 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
344 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
348 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
350 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
353 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
355 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
359 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
365 struct mvpp2_prs_entry pe; in mvpp2_prs_flow_find() local
376 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_flow_find()
377 bits = mvpp2_prs_sram_ai_get(&pe); in mvpp2_prs_flow_find()
410 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
414 mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL); in mvpp2_prs_mac_drop_all_set()
417 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_drop_all_set()
418 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
419 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
422 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
425 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
426 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
429 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
432 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
436 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
438 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
445 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
462 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_promisc_set()
464 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_promisc_set()
465 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
466 pe.index = tid; in mvpp2_prs_mac_promisc_set()
469 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
472 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK); in mvpp2_prs_mac_promisc_set()
475 mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match, in mvpp2_prs_mac_promisc_set()
479 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
483 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
486 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
490 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
492 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
499 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
512 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_set()
515 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_set()
516 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
517 pe.index = tid; in mvpp2_prs_dsa_tag_set()
520 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
524 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
530 mvpp2_prs_sram_ai_update(&pe, 1, in mvpp2_prs_dsa_tag_set()
533 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
537 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_dsa_tag_set()
540 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_dsa_tag_set()
543 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
547 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
549 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
553 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
557 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
559 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
566 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
583 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_ethertype_set()
586 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_ethertype_set()
587 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
588 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
591 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
592 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
594 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
597 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
601 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
605 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
610 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
613 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
616 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
618 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
621 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
625 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
627 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
633 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_find() local
646 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_find()
647 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid); in mvpp2_prs_vlan_find()
652 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_find()
656 ai_bits = mvpp2_prs_tcam_ai_get(&pe); in mvpp2_prs_vlan_find()
675 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_add() local
679 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
699 mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_vlan_add()
700 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_add()
709 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
710 pe.index = tid; in mvpp2_prs_vlan_add()
711 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
713 mvpp2_prs_match_etype(&pe, 0, tpid); in mvpp2_prs_vlan_add()
716 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_add()
719 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
722 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
726 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
729 mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
731 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
733 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_add()
736 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_vlan_add()
738 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_add()
760 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_find() local
773 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_find()
775 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) && in mvpp2_prs_double_vlan_find()
776 mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2); in mvpp2_prs_double_vlan_find()
781 ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
795 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_add() local
797 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
822 mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_double_vlan_add()
823 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_double_vlan_add()
833 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
834 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
835 pe.index = tid; in mvpp2_prs_double_vlan_add()
839 mvpp2_prs_match_etype(&pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
840 mvpp2_prs_match_etype(&pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
842 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
844 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
846 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
848 mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
851 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
853 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_add()
857 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_double_vlan_add()
858 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_double_vlan_add()
867 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
880 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_proto()
881 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
882 pe.index = tid; in mvpp2_prs_ip4_proto()
885 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
886 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_proto()
888 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_proto()
891 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
893 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); in mvpp2_prs_ip4_proto()
895 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, in mvpp2_prs_ip4_proto()
897 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, in mvpp2_prs_ip4_proto()
900 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
901 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
903 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
906 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
907 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
915 pe.index = tid; in mvpp2_prs_ip4_proto()
917 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
918 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
919 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
921 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, in mvpp2_prs_ip4_proto()
924 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); in mvpp2_prs_ip4_proto()
925 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); in mvpp2_prs_ip4_proto()
928 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
929 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
937 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
945 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_cast()
946 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
947 pe.index = tid; in mvpp2_prs_ip4_cast()
951 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
953 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
958 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
959 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
960 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
961 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
962 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
970 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_cast()
971 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_cast()
973 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
976 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
979 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
980 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
989 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
1001 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_proto()
1002 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1003 pe.index = tid; in mvpp2_prs_ip6_proto()
1006 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
1007 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
1008 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
1009 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
1013 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
1014 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
1017 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
1020 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1021 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
1029 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
1040 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_cast()
1041 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1042 pe.index = tid; in mvpp2_prs_ip6_cast()
1045 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1046 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
1048 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
1051 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
1053 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
1055 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
1057 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
1060 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1061 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
1096 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
1100 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow_init()
1101 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1102 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1105 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
1108 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1109 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
1112 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1113 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
1120 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
1122 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mh_init()
1124 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1125 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1126 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1128 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
1131 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
1134 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1135 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1143 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
1145 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_init()
1148 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1149 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1151 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
1153 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
1154 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
1157 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
1160 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1161 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
1172 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
1205 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_init()
1206 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
1207 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
1208 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
1211 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
1212 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
1215 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
1218 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
1220 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
1226 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_init() local
1228 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1231 pe.index = MVPP2_PE_VID_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1232 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1234 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT); in mvpp2_prs_vid_init()
1237 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vid_init()
1241 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1243 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1246 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1249 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1250 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1253 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1256 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1257 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1259 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT, in mvpp2_prs_vid_init()
1263 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN, in mvpp2_prs_vid_init()
1267 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1269 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1272 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1275 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1276 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1282 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
1291 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1292 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1293 pe.index = tid; in mvpp2_prs_etype_init()
1295 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
1297 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
1299 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
1300 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1304 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1305 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1306 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1307 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1309 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1317 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1318 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1319 pe.index = tid; in mvpp2_prs_etype_init()
1321 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
1324 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1325 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1326 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1329 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1334 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1335 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1336 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1337 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1339 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1347 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1348 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1349 pe.index = tid; in mvpp2_prs_etype_init()
1351 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
1354 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1355 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1356 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1361 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1366 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1367 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1368 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1369 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1373 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1381 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1382 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1383 pe.index = tid; in mvpp2_prs_etype_init()
1385 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
1386 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
1391 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
1392 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1395 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_etype_init()
1398 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1403 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1404 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1405 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1406 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1408 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1416 pe.index = tid; in mvpp2_prs_etype_init()
1418 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
1423 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_etype_init()
1424 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_etype_init()
1425 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
1429 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1430 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1431 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1432 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_etype_init()
1434 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1442 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1443 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1444 pe.index = tid; in mvpp2_prs_etype_init()
1446 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
1449 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
1452 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
1453 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1456 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1460 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1461 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1462 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1463 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1465 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1468 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
1469 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1470 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
1473 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
1476 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1477 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1478 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1481 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1486 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1487 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1488 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1489 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1491 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1505 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
1539 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1540 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1541 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
1543 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_init()
1546 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
1547 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
1550 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
1553 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1556 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1557 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1560 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1561 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1562 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
1564 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
1565 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
1569 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1572 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1573 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1581 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
1590 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1591 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1592 pe.index = tid; in mvpp2_prs_pppoe_init()
1594 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
1596 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
1597 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_pppoe_init()
1600 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
1603 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1608 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1609 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1617 pe.index = tid; in mvpp2_prs_pppoe_init()
1619 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
1625 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_pppoe_init()
1626 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_pppoe_init()
1627 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
1631 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1632 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1640 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1641 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1642 pe.index = tid; in mvpp2_prs_pppoe_init()
1644 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
1646 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
1647 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
1650 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, in mvpp2_prs_pppoe_init()
1653 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1658 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1659 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1667 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1668 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1669 pe.index = tid; in mvpp2_prs_pppoe_init()
1671 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
1675 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
1676 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
1678 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1683 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1684 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1692 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
1725 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1726 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1727 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
1730 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1731 mvpp2_prs_sram_shift_set(&pe, 12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
1733 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip4_init()
1736 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1738 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
1741 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
1743 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1746 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1747 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1750 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1751 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1752 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
1755 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
1756 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
1757 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
1760 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1763 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1766 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1767 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1775 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
1818 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1819 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1820 pe.index = tid; in mvpp2_prs_ip6_init()
1823 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1824 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1825 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
1830 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
1831 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1835 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1836 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1839 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1840 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1841 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
1844 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1845 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1846 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1849 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
1853 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1856 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1859 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1860 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1863 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1864 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1865 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
1868 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1869 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1870 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1873 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1876 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1879 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1880 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1883 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1884 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1885 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
1888 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1889 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
1891 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1894 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
1896 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
1898 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1901 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1902 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1912 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_range_find() local
1923 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vid_range_find()
1925 mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]); in mvpp2_prs_vid_range_find()
1926 mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]); in mvpp2_prs_vid_range_find()
1947 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_entry_add() local
1950 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_entry_add()
1973 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
1974 pe.index = tid; in mvpp2_prs_vid_entry_add()
1977 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_entry_add()
1979 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vid_entry_add()
1983 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_entry_add()
1986 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_entry_add()
1989 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_entry_add()
1992 mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid); in mvpp2_prs_vid_entry_add()
1995 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_entry_add()
1998 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
1999 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_entry_add()
2052 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_enable_filtering() local
2057 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_enable_filtering()
2059 pe.index = tid; in mvpp2_prs_vid_enable_filtering()
2067 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2070 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_enable_filtering()
2073 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_enable_filtering()
2076 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_enable_filtering()
2079 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_enable_filtering()
2082 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_vid_enable_filtering()
2086 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_enable_filtering()
2089 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2090 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_enable_filtering()
2161 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2168 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2184 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_range_find() local
2197 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_range_find()
2198 entry_pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_range_find()
2200 if (mvpp2_prs_mac_range_equals(&pe, da, mask) && in mvpp2_prs_mac_da_range_find()
2214 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_accept() local
2217 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_da_accept()
2236 pe.index = tid; in mvpp2_prs_mac_da_accept()
2239 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_da_accept()
2241 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_accept()
2244 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2247 mvpp2_prs_tcam_port_set(&pe, port->id, add); in mvpp2_prs_mac_da_accept()
2250 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_accept()
2255 mvpp2_prs_hw_inv(priv, pe.index); in mvpp2_prs_mac_da_accept()
2256 priv->prs_shadow[pe.index].valid = false; in mvpp2_prs_mac_da_accept()
2261 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
2266 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
2280 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2282 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2286 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
2290 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2291 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2292 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_da_accept()
2321 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_del_all() local
2334 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_del_all()
2336 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_del_all()
2344 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mac_del_all()
2411 struct mvpp2_prs_entry pe; in mvpp2_prs_add_flow() local
2415 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_add_flow()
2423 pe.index = tid; in mvpp2_prs_add_flow()
2428 mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_add_flow()
2429 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_add_flow()
2432 mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i], in mvpp2_prs_add_flow()
2436 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2437 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2438 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_add_flow()
2439 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_add_flow()
2447 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow() local
2450 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow()
2463 pe.index = tid; in mvpp2_prs_def_flow()
2466 mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2467 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
2470 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2472 mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_def_flow()
2475 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2476 mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id)); in mvpp2_prs_def_flow()
2477 mvpp2_prs_hw_write(port->priv, &pe); in mvpp2_prs_def_flow()