780 		for (rxq = 0; rxq < port->nrxqs; rxq++)  in mvpp2_swf_bm_pool_init()
793 		for (rxq = 0; rxq < port->nrxqs; rxq++)  in mvpp2_swf_bm_pool_init()
1454 	for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {  in mvpp2_defaults_set()
1472 	for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {  in mvpp2_ingress_enable()
1485 	for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {  in mvpp2_ingress_disable()
2367 	for (queue = 0; queue < port->nrxqs; queue++)  in mvpp2_cleanup_rxqs()
2376 	for (queue = 0; queue < port->nrxqs; queue++) {  in mvpp2_setup_rxqs()
3667 	for (queue = 0; queue < port->nrxqs; queue++) {  in mvpp2_ethtool_set_coalesce()
3846 		info->data = port->nrxqs;  in mvpp2_ethtool_get_rxnfc()
3968 	v->nrxqs = port->nrxqs;  in mvpp2_simple_queue_vectors_init()
4008 			v->nrxqs = MVPP2_DEFAULT_RXQ;  in mvpp2_multi_queue_vectors_init()
4012 			v->nrxqs = port->nrxqs;  in mvpp2_multi_queue_vectors_init()
4064 			    port->nrxqs);  in mvpp2_rx_irqs_setup()
4072 		if (!qv->nrxqs)  in mvpp2_rx_irqs_setup()
4080 		val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;  in mvpp2_rx_irqs_setup()
4094 	if (port->first_rxq + port->nrxqs >  in mvpp2_port_init()
4098 	if (port->nrxqs % MVPP2_DEFAULT_RXQ ||  in mvpp2_port_init()
4099 	    port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)  in mvpp2_port_init()
4143 	port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),  in mvpp2_port_init()
4151 	for (queue = 0; queue < port->nrxqs; queue++) {  in mvpp2_port_init()
4171 	for (queue = 0; queue < port->nrxqs; queue++) {  in mvpp2_port_init()
4604 	unsigned int ntxqs, nrxqs;  in mvpp2_port_probe()  local
4623 		nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus();  in mvpp2_port_probe()
4625 		nrxqs = MVPP2_DEFAULT_RXQ;  in mvpp2_port_probe()
4627 	dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);  in mvpp2_port_probe()
4665 	port->nrxqs = nrxqs;  in mvpp2_port_probe()
4690 		port->first_rxq = port->id * port->nrxqs;  in mvpp2_port_probe()