80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)  in mvpp2_read()  function
359 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));  in mvpp2_bm_pool_create()
452 	buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &  in mvpp2_check_hw_buf_num()
454 	buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &  in mvpp2_check_hw_buf_num()
483 	val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));  in mvpp2_bm_pool_destroy()
571 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_long_pool_set()
592 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_short_pool_set()
1440 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);  in mvpp2_defaults_set()
1456 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_defaults_set()
1474 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_ingress_enable()
1487 		val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));  in mvpp2_ingress_disable()
1526 	reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &  in mvpp2_egress_disable()
1547 		reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);  in mvpp2_egress_disable()
1557 	u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));  in mvpp2_rxq_received()
1597 	val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));  in mvpp2_rxq_offset_set()
1815 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);  in mvpp2_txp_max_tx_size_set()
1821 	val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);  in mvpp2_txp_max_tx_size_set()
1831 		val = mvpp2_read(port->priv,  in mvpp2_txp_max_tx_size_set()
2035 	aggr_txq->next_desc_to_proc = mvpp2_read(priv,  in mvpp2_aggr_txq_init()
2207 	val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));  in mvpp2_txq_init()
2344 	val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);  in mvpp2_cleanup_txqs()