541 			hw_dbg("PHY module has not been recognized\n");  in igb_set_sfp_media_type_82575()
772 		hw_dbg("PHY Address %u is out of range\n", offset);  in igb_read_phy_reg_sgmii_82575()
804 		hw_dbg("PHY Address %d is out of range\n", offset);  in igb_write_phy_reg_sgmii_82575()
888 			hw_dbg("Vendor ID 0x%08X read at address %u\n",  in igb_get_phy_id_82575()
896 			hw_dbg("PHY address %u was unreadable\n", phy->addr);  in igb_get_phy_id_82575()
931 	hw_dbg("Soft resetting SGMII attached PHY...\n");  in igb_phy_hw_reset_sgmii_82575()
1188 		hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");  in igb_acquire_swfw_sync_82575()
1253 		hw_dbg("MNG configuration cycle has not completed.\n");  in igb_get_cfg_done_82575()
1316 			hw_dbg("Error configuring flow control\n");  in igb_check_for_link_82575()
1406 				hw_dbg("2500 Mbs, ");  in igb_get_pcs_speed_and_duplex_82575()
1407 				hw_dbg("Full Duplex\n");  in igb_get_pcs_speed_and_duplex_82575()
1465 		hw_dbg("PCI-E Master disable polling has failed.\n");  in igb_reset_hw_82575()
1470 		hw_dbg("PCI-E Set completion timeout has failed.\n");  in igb_reset_hw_82575()
1472 	hw_dbg("Masking off all interrupts\n");  in igb_reset_hw_82575()
1483 	hw_dbg("Issuing a global reset to MAC\n");  in igb_reset_hw_82575()
1492 		hw_dbg("Auto Read Done did not complete\n");  in igb_reset_hw_82575()
1531 		hw_dbg("Error initializing identification LED\n");  in igb_init_hw_82575()
1536 	hw_dbg("Initializing the IEEE VLAN\n");  in igb_init_hw_82575()
1543 	hw_dbg("Zeroing the MTA\n");  in igb_init_hw_82575()
1548 	hw_dbg("Zeroing the UTA\n");  in igb_init_hw_82575()
1607 			hw_dbg("Error resetting the PHY.\n");  in igb_setup_copper_link_82575()
1717 				hw_dbg(KERN_DEBUG "NVM Read Error\n\n");  in igb_setup_serdes_link_82575()
1772 		hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);  in igb_setup_serdes_link_82575()
1780 		hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);  in igb_setup_serdes_link_82575()
1815 		hw_dbg("Running reset init script for 82575\n");  in igb_reset_init_script_82575()
1980 		hw_dbg("Queue disable timed out after 10ms\n");  in igb_rx_fifo_flush_82575()
2233 		hw_dbg("NVM Read Error\n");  in igb_reset_mdicnfg_82580()
2278 		hw_dbg("PCI-E Master disable polling has failed.\n");  in igb_reset_hw_82580()
2280 	hw_dbg("Masking off all interrupts\n");  in igb_reset_hw_82580()
2312 		hw_dbg("Auto Read Done did not complete\n");  in igb_reset_hw_82580()
2324 		hw_dbg("Could not reset MDICNFG based on EEPROM\n");  in igb_reset_hw_82580()
2375 			hw_dbg("NVM Read Error\n");  in igb_validate_nvm_checksum_with_offset()
2382 		hw_dbg("NVM Checksum Invalid\n");  in igb_validate_nvm_checksum_with_offset()
2410 			hw_dbg("NVM Read Error while updating checksum.\n");  in igb_update_nvm_checksum_with_offset()
2419 		hw_dbg("NVM Write Error while updating checksum.\n");  in igb_update_nvm_checksum_with_offset()
2442 		hw_dbg("NVM Read Error\n");  in igb_validate_nvm_checksum_82580()
2481 		hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");  in igb_update_nvm_checksum_82580()
2491 			hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");  in igb_update_nvm_checksum_82580()
2631 			hw_dbg("LPI Clock Stop Bit should not be set!\n");  in igb_set_eee_i350()