22 		hw->aq.asq.tail = I40E_VF_ATQT1;  in i40e_adminq_init_regs()
23 		hw->aq.asq.head = I40E_VF_ATQH1;  in i40e_adminq_init_regs()
24 		hw->aq.asq.len  = I40E_VF_ATQLEN1;  in i40e_adminq_init_regs()
25 		hw->aq.asq.bal  = I40E_VF_ATQBAL1;  in i40e_adminq_init_regs()
26 		hw->aq.asq.bah  = I40E_VF_ATQBAH1;  in i40e_adminq_init_regs()
33 		hw->aq.asq.tail = I40E_PF_ATQT;  in i40e_adminq_init_regs()
34 		hw->aq.asq.head = I40E_PF_ATQH;  in i40e_adminq_init_regs()
35 		hw->aq.asq.len  = I40E_PF_ATQLEN;  in i40e_adminq_init_regs()
36 		hw->aq.asq.bal  = I40E_PF_ATQBAL;  in i40e_adminq_init_regs()
37 		hw->aq.asq.bah  = I40E_PF_ATQBAH;  in i40e_adminq_init_regs()
54 	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,  in i40e_alloc_adminq_asq_ring()
62 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,  in i40e_alloc_adminq_asq_ring()
66 		i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);  in i40e_alloc_adminq_asq_ring()
99 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);  in i40e_free_adminq_asq()
192 	ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,  in i40e_alloc_asq_bufs()
196 	hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;  in i40e_alloc_asq_bufs()
200 		bi = &hw->aq.asq.r.asq_bi[i];  in i40e_alloc_asq_bufs()
215 		i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);  in i40e_alloc_asq_bufs()
216 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);  in i40e_alloc_asq_bufs()
250 		if (hw->aq.asq.r.asq_bi[i].pa)  in i40e_free_asq_bufs()
251 			i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);  in i40e_free_asq_bufs()
254 	i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);  in i40e_free_asq_bufs()
257 	i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);  in i40e_free_asq_bufs()
260 	i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);  in i40e_free_asq_bufs()
275 	wr32(hw, hw->aq.asq.head, 0);  in i40e_config_asq_regs()
276 	wr32(hw, hw->aq.asq.tail, 0);  in i40e_config_asq_regs()
279 	wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |  in i40e_config_asq_regs()
281 	wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));  in i40e_config_asq_regs()
282 	wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));  in i40e_config_asq_regs()
285 	reg = rd32(hw, hw->aq.asq.bal);  in i40e_config_asq_regs()
286 	if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))  in i40e_config_asq_regs()
341 	if (hw->aq.asq.count > 0) {  in i40e_init_asq()
354 	hw->aq.asq.next_to_use = 0;  in i40e_init_asq()
355 	hw->aq.asq.next_to_clean = 0;  in i40e_init_asq()
373 	hw->aq.asq.count = hw->aq.num_asq_entries;  in i40e_init_asq()
454 	if (hw->aq.asq.count == 0) {  in i40e_shutdown_asq()
460 	wr32(hw, hw->aq.asq.head, 0);  in i40e_shutdown_asq()
461 	wr32(hw, hw->aq.asq.tail, 0);  in i40e_shutdown_asq()
462 	wr32(hw, hw->aq.asq.len, 0);  in i40e_shutdown_asq()
463 	wr32(hw, hw->aq.asq.bal, 0);  in i40e_shutdown_asq()
464 	wr32(hw, hw->aq.asq.bah, 0);  in i40e_shutdown_asq()
466 	hw->aq.asq.count = 0; /* to indicate uninitialized queue */  in i40e_shutdown_asq()
658 	struct i40e_adminq_ring *asq = &(hw->aq.asq);  in i40e_clean_asq()  local
660 	u16 ntc = asq->next_to_clean;  in i40e_clean_asq()
664 	desc = I40E_ADMINQ_DESC(*asq, ntc);  in i40e_clean_asq()
665 	details = I40E_ADMINQ_DETAILS(*asq, ntc);  in i40e_clean_asq()
666 	while (rd32(hw, hw->aq.asq.head) != ntc) {  in i40e_clean_asq()
668 			   "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));  in i40e_clean_asq()
679 		if (ntc == asq->count)  in i40e_clean_asq()
681 		desc = I40E_ADMINQ_DESC(*asq, ntc);  in i40e_clean_asq()
682 		details = I40E_ADMINQ_DETAILS(*asq, ntc);  in i40e_clean_asq()
685 	asq->next_to_clean = ntc;  in i40e_clean_asq()
687 	return I40E_DESC_UNUSED(asq);  in i40e_clean_asq()
702 	return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;  in i40e_asq_done()
733 	if (hw->aq.asq.count == 0) {  in i40e_asq_send_command()
742 	val = rd32(hw, hw->aq.asq.head);  in i40e_asq_send_command()
750 	details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);  in i40e_asq_send_command()
805 	desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);  in i40e_asq_send_command()
812 		dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);  in i40e_asq_send_command()
830 	(hw->aq.asq.next_to_use)++;  in i40e_asq_send_command()
831 	if (hw->aq.asq.next_to_use == hw->aq.asq.count)  in i40e_asq_send_command()
832 		hw->aq.asq.next_to_use = 0;  in i40e_asq_send_command()
834 		wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);  in i40e_asq_send_command()
889 		if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {  in i40e_asq_send_command()
1028 	hw->aq.asq.next_to_use = 0;  in i40e_resume_aq()
1029 	hw->aq.asq.next_to_clean = 0;  in i40e_resume_aq()