122 	void __iomem *glb_base;  member
142 	val = readl(priv->glb_base + GLB_IRQ_ENA);  in hisi_femac_irq_enable()
143 	writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);  in hisi_femac_irq_enable()
150 	val = readl(priv->glb_base + GLB_IRQ_ENA);  in hisi_femac_irq_disable()
151 	writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);  in hisi_femac_irq_disable()
266 	while (readl(priv->glb_base + GLB_IRQ_RAW) & IRQ_INT_RX_RDY) {  in hisi_femac_rx()
272 		writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_rx()
327 		ints = readl(priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_poll()
329 		       priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_poll()
347 	ints = readl(priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_interrupt()
351 		       priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_interrupt()
447 	writel(reg, priv->glb_base + GLB_HOSTMAC_H16);  in hisi_femac_set_hw_mac_addr()
450 	writel(reg, priv->glb_base + GLB_HOSTMAC_L32);  in hisi_femac_set_hw_mac_addr()
459 	val = readl(priv->glb_base + GLB_SOFT_RESET);  in hisi_femac_port_reset()
461 	writel(val, priv->glb_base + GLB_SOFT_RESET);  in hisi_femac_port_reset()
466 	writel(val, priv->glb_base + GLB_SOFT_RESET);  in hisi_femac_port_reset()
488 	writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_net_open()
583 	val = readl(priv->glb_base + GLB_MAC_H16(reg_n));  in hisi_femac_enable_hw_addr_filter()
588 	writel(val, priv->glb_base + GLB_MAC_H16(reg_n));  in hisi_femac_enable_hw_addr_filter()
602 	writel(val, priv->glb_base + low);  in hisi_femac_set_hw_addr_filter()
604 	val = readl(priv->glb_base + high);  in hisi_femac_set_hw_addr_filter()
608 	writel(val, priv->glb_base + high);  in hisi_femac_set_hw_addr_filter()
616 	val = readl(priv->glb_base + GLB_FWCTRL);  in hisi_femac_set_promisc_mode()
621 	writel(val, priv->glb_base + GLB_FWCTRL);  in hisi_femac_set_promisc_mode()
630 	val = readl(priv->glb_base + GLB_MACTCTRL);  in hisi_femac_set_mc_addr_filter()
648 	writel(val, priv->glb_base + GLB_MACTCTRL);  in hisi_femac_set_mc_addr_filter()
657 	val = readl(priv->glb_base + GLB_MACTCTRL);  in hisi_femac_set_uc_addr_filter()
674 	writel(val, priv->glb_base + GLB_MACTCTRL);  in hisi_femac_set_uc_addr_filter()
767 	writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);  in hisi_femac_port_init()
770 	val = readl(priv->glb_base + GLB_FWCTRL);  in hisi_femac_port_init()
773 	writel(val, priv->glb_base + GLB_FWCTRL);  in hisi_femac_port_init()
775 	val = readl(priv->glb_base + GLB_MACTCTRL);  in hisi_femac_port_init()
777 	writel(val, priv->glb_base + GLB_MACTCTRL);  in hisi_femac_port_init()
822 	priv->glb_base = devm_ioremap_resource(dev, res);  in hisi_femac_drv_probe()
823 	if (IS_ERR(priv->glb_base)) {  in hisi_femac_drv_probe()
824 		ret = PTR_ERR(priv->glb_base);  in hisi_femac_drv_probe()