196 	u32 tctrl;		/* 0x040 Transmit control register */  member
873 		iowrite32be(ioread32be(&regs->tctrl) &  in graceful_start()
874 				~TCTRL_GTS, &regs->tctrl);  in graceful_start()
905 			tmp = ioread32be(&regs->tctrl) | TCTRL_GTS;  in graceful_stop()
906 			iowrite32be(tmp, &regs->tctrl);  in graceful_stop()
972 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_set_tx_pause_frames()
1013 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_accept_rx_pause_frames()
1040 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_modify_mac_address()
1144 	u32 rctrl, tctrl;  in dtsec_set_tstamp()  local
1150 	tctrl = ioread32be(&regs->tctrl);  in dtsec_set_tstamp()
1154 		tctrl |= TCTRL_TTSE;  in dtsec_set_tstamp()
1157 		tctrl &= ~TCTRL_TTSE;  in dtsec_set_tstamp()
1161 	iowrite32be(tctrl, &regs->tctrl);  in dtsec_set_tstamp()
1277 	if ((ioread32be(&regs->tctrl) & TCTRL_GTS) == 0)  in dtsec_adjust_link()