198 	u32 rctrl;		/* 0x050 Receive control register */  member
433 	iowrite32be(tmp, &regs->rctrl);  in init()
763 				iowrite32be(ioread32be(&regs->rctrl) |  in dtsec_isr()
764 					    RCTRL_GRS, &regs->rctrl);  in dtsec_isr()
876 		iowrite32be(ioread32be(&regs->rctrl) &  in graceful_start()
877 				~RCTRL_GRS, &regs->rctrl);  in graceful_start()
887 		tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;  in graceful_stop()
888 		iowrite32be(tmp, &regs->rctrl);  in graceful_stop()
970 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_set_tx_pause_frames()
1011 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_accept_rx_pause_frames()
1038 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_modify_mac_address()
1070 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_add_hash_mac_address()
1130 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_allmulti()
1136 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_allmulti()
1144 	u32 rctrl, tctrl;  in dtsec_set_tstamp()  local
1149 	rctrl = ioread32be(&regs->rctrl);  in dtsec_set_tstamp()
1153 		rctrl |= RCTRL_RTSE;  in dtsec_set_tstamp()
1156 		rctrl &= ~RCTRL_RTSE;  in dtsec_set_tstamp()
1160 	iowrite32be(rctrl, &regs->rctrl);  in dtsec_set_tstamp()
1181 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);  in dtsec_del_hash_mac_address()
1246 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1252 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1255 	tmp = ioread32be(&regs->rctrl);  in dtsec_set_promiscuous()
1261 	iowrite32be(tmp, &regs->rctrl);  in dtsec_set_promiscuous()
1275 	if ((ioread32be(&regs->rctrl) & RCTRL_GRS) == 0)  in dtsec_adjust_link()