178 iow(struct board_info *db, int reg, int value)  in iow()  function
193 	iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);  in dm9000_reset()
198 	iow(db, DM9000_NCR, 0);  in dm9000_reset()
199 	iow(db, DM9000_NCR, NCR_RST | NCR_MAC_LBK);  in dm9000_reset()
302 	iow(db, DM9000_EPAR, DM9000_PHY | reg);  in dm9000_phy_read()
305 	iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);  in dm9000_phy_read()
315 	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer read command */  in dm9000_phy_read()
349 	iow(db, DM9000_EPAR, DM9000_PHY | reg);  in dm9000_phy_write()
352 	iow(db, DM9000_EPDRL, value);  in dm9000_phy_write()
353 	iow(db, DM9000_EPDRH, value >> 8);  in dm9000_phy_write()
356 	iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);  in dm9000_phy_write()
366 	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer write command */  in dm9000_phy_write()
493 	iow(db, DM9000_EPAR, offset);  in dm9000_read_eeprom()
494 	iow(db, DM9000_EPCR, EPCR_ERPRR);  in dm9000_read_eeprom()
505 	iow(db, DM9000_EPCR, 0x0);  in dm9000_read_eeprom()
529 	iow(db, DM9000_EPAR, offset);  in dm9000_write_eeprom()
530 	iow(db, DM9000_EPDRH, data[1]);  in dm9000_write_eeprom()
531 	iow(db, DM9000_EPDRL, data[0]);  in dm9000_write_eeprom()
532 	iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);  in dm9000_write_eeprom()
540 	iow(db, DM9000_EPCR, 0);  in dm9000_write_eeprom()
607 	iow(dm, DM9000_RCSR, (features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);  in dm9000_set_features()
726 	iow(dm, DM9000_WCR, wcr);  in dm9000_set_wol()
860 		iow(db, oft, dev->dev_addr[i]);  in dm9000_hash_table_unlocked()
876 		iow(db, oft++, hash_table[i]);  in dm9000_hash_table_unlocked()
877 		iow(db, oft++, hash_table[i] >> 8);  in dm9000_hash_table_unlocked()
880 	iow(db, DM9000_RCR, rcr);  in dm9000_hash_table_unlocked()
897 	iow(db, DM9000_IMR, IMR_PAR);  in dm9000_mask_interrupts()
903 	iow(db, DM9000_IMR, db->imr_all);  in dm9000_unmask_interrupts()
926 		iow(db, DM9000_RCSR,  in dm9000_init_dm9000()
929 	iow(db, DM9000_GPCR, GPCR_GEP_CNTL);	/* Let GPIO0 output */  in dm9000_init_dm9000()
930 	iow(db, DM9000_GPR, 0);  in dm9000_init_dm9000()
948 	iow(db, DM9000_NCR, ncr);  in dm9000_init_dm9000()
951 	iow(db, DM9000_TCR, 0);	        /* TX Polling clear */  in dm9000_init_dm9000()
952 	iow(db, DM9000_BPTR, 0x3f);	/* Less 3Kb, 200us */  in dm9000_init_dm9000()
953 	iow(db, DM9000_FCR, 0xff);	/* Flow Control */  in dm9000_init_dm9000()
954 	iow(db, DM9000_SMCR, 0);        /* Special Mode */  in dm9000_init_dm9000()
956 	iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);  in dm9000_init_dm9000()
957 	iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */  in dm9000_init_dm9000()
1008 			iow(dm, DM9000_TCCR, 0);  in dm9000_send_packet()
1010 			iow(dm, DM9000_TCCR, TCCR_IP | TCCR_UDP | TCCR_TCP);  in dm9000_send_packet()
1015 	iow(dm, DM9000_TXPLL, pkt_len);  in dm9000_send_packet()
1016 	iow(dm, DM9000_TXPLH, pkt_len >> 8);  in dm9000_send_packet()
1019 	iow(dm, DM9000_TCR, TCR_TXREQ);	/* Cleared after TX complete */  in dm9000_send_packet()
1118 			iow(db, DM9000_RCR, 0x00);	/* Stop Device */  in dm9000_rx()
1221 	iow(db, DM9000_ISR, int_status);	/* Clear ISR status */  in dm9000_interrupt()
1266 		iow(db, DM9000_NSR, NSR_WAKEST);  in dm9000_wol_interrupt()
1318 	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */  in dm9000_open()
1350 	iow(db, DM9000_GPR, 0x01);	/* Power-Down PHY */  in dm9000_shutdown()
1352 	iow(db, DM9000_RCR, 0x00);	/* Disable RX */  in dm9000_shutdown()