Lines Matching defs:adapter_params

361 struct adapter_params {  struct
362 	struct sge_params sge;
363 	struct tp_params  tp;
364 	struct vpd_params vpd;
365 	struct pf_resources pfres;
366 	struct pci_params pci;
367 	struct devlog_params devlog;
368 	enum pcie_memwin drv_memwin;
370 	unsigned int cim_la_size;
372 	unsigned int sf_size;             /* serial flash size in bytes */
373 	unsigned int sf_nsec;             /* # of flash sectors */
375 	unsigned int fw_vers;		  /* firmware version */
376 	unsigned int bs_vers;		  /* bootstrap version */
377 	unsigned int tp_vers;		  /* TP microcode version */
378 	unsigned int er_vers;		  /* expansion ROM version */
379 	unsigned int scfg_vers;		  /* Serial Configuration version */
380 	unsigned int vpd_vers;		  /* VPD Version */
381 	u8 api_vers[7];
383 	unsigned short mtus[NMTUS];
384 	unsigned short a_wnd[NCCTRL_WIN];
385 	unsigned short b_wnd[NCCTRL_WIN];
387 	unsigned char nports;             /* # of ethernet ports */
388 	unsigned char portvec;
389 	enum chip_type chip;               /* chip code */
390 	struct arch_specific_params arch;  /* chip specific params */
391 	unsigned char offload;
392 	unsigned char crypto;		/* HW capability for crypto */
394 	unsigned char bypass;
395 	unsigned char hash_filter;
397 	unsigned int ofldq_wr_cred;
398 	bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
400 	unsigned int nsched_cls;          /* number of traffic classes */
401 	unsigned int max_ordird_qp;       /* Max read depth per RDMA QP */
402 	unsigned int max_ird_adapter;     /* Max read depth per adapter */
403 	bool fr_nsmr_tpte_wr_support;	  /* FW support for FR_NSMR_TPTE_WR */
404 	u8 fw_caps_support;		/* 32-bit Port Capabilities */
405 	bool filter2_wr_support;	/* FW support for FILTER2_WR */
410 	u8 mps_bg_map[MAX_NPORTS];	/* MPS Buffer Group Map */
411 	bool write_w_imm_support;       /* FW supports WRITE_WITH_IMMEDIATE */
412 	bool write_cmpl_support;        /* FW supports WRITE_CMPL */