Lines Matching refs:BIT_ULL
39 #define CMR_PKT_TX_EN BIT_ULL(13)
40 #define CMR_PKT_RX_EN BIT_ULL(14)
41 #define CMR_EN BIT_ULL(15)
43 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
60 #define RX_DMACX_CAM_EN BIT_ULL(48)
90 #define SPU_CTL_LOW_POWER BIT_ULL(11)
91 #define SPU_CTL_LOOPBACK BIT_ULL(14)
92 #define SPU_CTL_RESET BIT_ULL(15)
94 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
96 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
98 #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12)
100 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0)
101 #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12)
103 #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1)
108 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0)
109 #define SPU_FEC_CTL_ERR_EN BIT_ULL(1)
111 #define SPU_AN_CTL_AN_EN BIT_ULL(12)
112 #define SPU_AN_CTL_XNP_EN BIT_ULL(13)
115 #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10)
116 #define SPU_MISC_CTL_RX_DIS BIT_ULL(12)
122 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18)
123 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29)
127 #define BGX_PKT_RX_PTP_EN BIT_ULL(12)
132 #define SMU_TX_APPEND_FCS_D BIT_ULL(2)
139 #define SMU_TX_CTL_DIC_EN BIT_ULL(0)
140 #define SMU_TX_CTL_UNI_EN BIT_ULL(1)
144 #define SMU_CTL_RX_IDLE BIT_ULL(0)
145 #define SMU_CTL_TX_IDLE BIT_ULL(1)
147 #define RX_EN BIT_ULL(0)
148 #define TX_EN BIT_ULL(1)
149 #define BCK_EN BIT_ULL(2)
150 #define DRP_EN BIT_ULL(3)
153 #define PCS_MRX_CTL_RST_AN BIT_ULL(9)
154 #define PCS_MRX_CTL_PWR_DN BIT_ULL(11)
155 #define PCS_MRX_CTL_AN_EN BIT_ULL(12)
156 #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14)
157 #define PCS_MRX_CTL_RESET BIT_ULL(15)
159 #define PCS_MRX_STATUS_LINK BIT_ULL(2)
160 #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5)
167 #define PCS_MISC_CTL_MODE BIT_ULL(8)
168 #define PCS_MISC_CTL_DISP_EN BIT_ULL(13)
169 #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11)
172 #define GMI_PORT_CFG_SPEED BIT_ULL(1)
173 #define GMI_PORT_CFG_DUPLEX BIT_ULL(2)
174 #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3)
175 #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8)
176 #define GMI_PORT_CFG_RX_IDLE BIT_ULL(12)
177 #define GMI_PORT_CFG_TX_IDLE BIT_ULL(13)