Lines Matching refs:tr32
632 #define tr32(reg) tp->read32(tp, reg) macro
678 *val = tr32(TG3PCI_MEM_WIN_DATA); in tg3_read_mem()
1100 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); in tg3_switch_clocks()
1155 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1159 frame_val = tr32(MAC_MI_COM); in __tg3_readphy()
1217 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1220 frame_val = tr32(MAC_MI_COM); in __tg3_writephy()
1449 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1468 val = tr32(MAC_PHYCFG1); in tg3_mdio_config_5785()
1481 val = tr32(MAC_EXT_RGMII_MODE); in tg3_mdio_config_5785()
1526 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; in tg3_mdio_init()
1528 is_serdes = tr32(TG3_CPMU_PHY_STRAP) & in tg3_mdio_init()
1635 val = tr32(GRC_RX_CPU_EVENT); in tg3_generate_fw_event()
1665 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) in tg3_wait_for_event_ack()
1839 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) in tg3_poll_fw()
2394 val = tr32(TG3_CPMU_EEE_MODE); in tg3_eee_pull_config()
2398 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2436 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_adjust()
2456 val = tr32(TG3_CPMU_EEE_MODE); in tg3_phy_eee_enable()
2654 val = tr32(GRC_MISC_CFG); in tg3_phy_reset()
2680 cpmuctrl = tr32(TG3_CPMU_CTRL); in tg3_phy_reset()
2699 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_phy_reset()
2813 status = tr32(TG3_CPMU_DRV_STATUS); in tg3_set_function_status()
3084 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_power_down_phy()
3085 u32 serdes_cfg = tr32(MAC_SERDES_CFG); in tg3_power_down_phy()
3097 val = tr32(GRC_MISC_CFG); in tg3_power_down_phy()
3140 val = tr32(TG3_CPMU_LSPD_1000MB_CLK); in tg3_power_down_phy()
3158 if (tr32(NVRAM_SWARB) & SWARB_GNT1) in tg3_nvram_lock()
3187 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_enable_nvram_access()
3197 u32 nvaccess = tr32(NVRAM_ACCESS); in tg3_disable_nvram_access()
3212 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | in tg3_nvram_read_using_eeprom()
3223 tmp = tr32(GRC_EEPROM_ADDR); in tg3_nvram_read_using_eeprom()
3232 tmp = tr32(GRC_EEPROM_DATA); in tg3_nvram_read_using_eeprom()
3252 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { in tg3_nvram_exec_cmd()
3323 *val = tr32(NVRAM_RDDATA); in tg3_nvram_read()
3364 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3376 val = tr32(GRC_EEPROM_ADDR); in tg3_nvram_write_block_using_eeprom()
3569 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3580 grc_mode = tr32(GRC_MODE); in tg3_nvram_write_block()
3609 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT) in tg3_pause_cpu()
3657 u32 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_halt_cpu()
3750 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT); in tg3_load_firmware_cpu()
3790 if (tr32(cpu_base + CPU_PC) == pc) in tg3_pause_cpu_and_set_pc()
3833 tr32(RX_CPU_BASE + CPU_PC), in tg3_load_5701_a0_firmware_fix()
3853 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP) in tg3_validate_rxcpu_state()
3956 __func__, tr32(cpu_base + CPU_PC), in tg3_load_tso_firmware()
4053 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_power_down_prepare()
4117 val = tr32(GRC_VCPU_EXT_CTRL); in tg3_power_down_prepare()
4258 u32 val = tr32(0x7d00); in tg3_power_down_prepare()
4361 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE); in tg3_phy_autoneg_cfg()
5016 u32 led_ctrl = tr32(MAC_LED_CTRL); in tg3_setup_copper_phy()
5181 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { in tg3_fiber_aneg_smachine()
5182 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); in tg3_fiber_aneg_smachine()
5460 u32 mac_status = tr32(MAC_STATUS); in tg3_init_bcm8002()
5525 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_setup_fiber_hw_autoneg()
5530 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; in tg3_setup_fiber_hw_autoneg()
5533 sg_dig_ctrl = tr32(SG_DIG_CTRL); in tg3_setup_fiber_hw_autoneg()
5586 sg_dig_status = tr32(SG_DIG_STATUS); in tg3_setup_fiber_hw_autoneg()
5587 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5631 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_hw_autoneg()
5690 if ((tr32(MAC_STATUS) & in tg3_setup_fiber_by_hand()
5696 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_by_hand()
5734 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5763 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5778 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | in tg3_setup_fiber_phy()
5784 mac_status = tr32(MAC_STATUS); in tg3_setup_fiber_phy()
5883 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
5952 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_setup_fiber_mii_phy()
6090 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; in tg3_setup_phy()
6098 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; in tg3_setup_phy()
6107 val |= tr32(MAC_TX_LENGTHS) & in tg3_setup_phy()
6129 val = tr32(PCIE_PWR_MGMT_THRESH); in tg3_setup_phy()
6144 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB); in tg3_refclk_read()
6145 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32; in tg3_refclk_read()
6151 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_refclk_write()
6280 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL); in tg3_ptp_enable()
6393 *dst++ = tr32(off + i); in tg3_rd32_loop()
6458 regs[i / sizeof(u32)] = tr32(i); in tg3_dump_state()
6560 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB); in tg3_tx()
6561 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32; in tg3_tx()
6873 tstamp = tr32(TG3_RX_TSTAMP_LSB); in tg3_rx()
6874 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32; in tg3_rx()
7297 val = tr32(HOSTCC_FLOW_ATTN); in tg3_process_error()
7303 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) { in tg3_process_error()
7308 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) { in tg3_process_error()
7525 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt()
7574 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_interrupt_tagged()
7620 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { in tg3_test_isr()
8848 val = tr32(ofs); in tg3_stop_block()
8862 val = tr32(ofs); in tg3_stop_block()
8919 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) in tg3_abort_hw()
8925 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); in tg3_abort_hw()
9010 val = tr32(MSGINT_MODE); in tg3_restore_pci_state()
9022 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_override_clk()
9043 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_restore_clk()
9050 val = tr32(TG3_CPMU_CLCK_ORIDE); in tg3_restore_clk()
9126 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_chip_reset()
9137 tr32(TG3_PCIE_PHY_TSTCTL) == in tg3_chip_reset()
9148 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); in tg3_chip_reset()
9150 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); in tg3_chip_reset()
9235 val = tr32(MEMARB_MODE); in tg3_chip_reset()
9260 val = tr32(0xc4); in tg3_chip_reset()
9293 val = tr32(0x7c00); in tg3_chip_reset()
9304 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE); in tg3_chip_reset()
9388 addr0_high = tr32(MAC_ADDR_0_HIGH); in tg3_set_mac_addr()
9389 addr0_low = tr32(MAC_ADDR_0_LOW); in tg3_set_mac_addr()
9390 addr1_high = tr32(MAC_ADDR_1_HIGH); in tg3_set_mac_addr()
9391 addr1_low = tr32(MAC_ADDR_1_LOW); in tg3_set_mac_addr()
9902 val = tr32(TG3_CPMU_CTRL); in tg3_reset_hw()
9906 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
9911 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); in tg3_reset_hw()
9916 val = tr32(TG3_CPMU_HST_ACC); in tg3_reset_hw()
9923 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; in tg3_reset_hw()
9928 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; in tg3_reset_hw()
9933 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; in tg3_reset_hw()
9938 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9944 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); in tg3_reset_hw()
9953 u32 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9959 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9971 val = tr32(TG3_CPMU_PADRNG_CTL); in tg3_reset_hw()
9975 grc_mode = tr32(GRC_MODE); in tg3_reset_hw()
9981 val = tr32(TG3_PCIE_TLDLPL_PORT + in tg3_reset_hw()
9990 val = tr32(TG3_CPMU_LSPD_10MB_CLK); in tg3_reset_hw()
10009 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
10018 val = tr32(TG3PCI_PCISTATE); in tg3_reset_hw()
10027 val = tr32(TG3PCI_MSI_DATA); in tg3_reset_hw()
10042 val = tr32(TG3PCI_DMA_RW_CTRL) & in tg3_reset_hw()
10089 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK; in tg3_reset_hw()
10094 val = tr32(GRC_MISC_CFG); in tg3_reset_hw()
10151 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) in tg3_reset_hw()
10161 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
10256 val |= tr32(MAC_TX_LENGTHS) & in tg3_reset_hw()
10290 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10319 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; in tg3_reset_hw()
10333 val = tr32(tgtreg); in tg3_reset_hw()
10356 val = tr32(tgtreg); in tg3_reset_hw()
10364 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10369 val = tr32(RCVLPC_STATS_ENABLE); in tg3_reset_hw()
10384 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) in tg3_reset_hw()
10460 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10471 val = tr32(MSGINT_MODE); in tg3_reset_hw()
10497 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && in tg3_reset_hw()
10535 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10539 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_reset_hw()
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10652 val = tr32(MAC_SERDES_CFG); in tg3_reset_hw()
10680 tmp = tr32(SERDES_RX_CTRL); in tg3_reset_hw()
10889 do { u32 __val = tr32(REG); \
10920 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL); in tg3_periodic_fetch_stats()
10948 u32 val = tr32(HOSTCC_FLOW_ATTN); in tg3_periodic_fetch_stats()
11001 tr32(HOSTCC_MODE); in tg3_timer()
11017 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_timer()
11036 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11048 u32 mac_stat = tr32(MAC_STATUS); in tg3_timer()
11075 u32 cpmu = tr32(TG3_CPMU_STATUS); in tg3_timer()
11291 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11310 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); in tg3_test_interrupt()
11337 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; in tg3_test_interrupt()
11531 u32 msi_mode = tr32(MSGINT_MODE); in tg3_ints_init()
11630 u32 val = tr32(PCIE_TRANSACTION_CFG); in tg3_start()
12012 cpmu_val = tr32(TG3_CPMU_CTRL); in tg3_get_eeprom()
13273 save_val = tr32(offset); in tg3_test_registers()
13283 val = tr32(offset); in tg3_test_registers()
13295 val = tr32(offset); in tg3_test_registers()
13711 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) in tg3_test_loopback()
14389 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_nvram_info()
14467 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5752_nvram_info()
14508 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5755_nvram_info()
14564 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5787_nvram_info()
14602 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5761_nvram_info()
14642 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14684 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_57780_nvram_info()
14757 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5717_nvram_info()
14835 nvcfg1 = tr32(NVRAM_CFG1); in tg3_get_5720_nvram_info()
14855 nv_status = tr32(NVRAM_AUTOSENSE_STATUS); in tg3_get_5720_nvram_info()
15015 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); in tg3_nvram_init()
15165 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { in tg3_get_eeprom_hw_cfg()
15169 val = tr32(VCPU_CFGSHDW); in tg3_get_eeprom_hw_cfg()
15413 val = tr32(OTP_STATUS); in tg3_issue_otp_command()
15440 thalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
15447 bhalf_otp = tr32(OTP_READ_DATA); in tg3_read_otp_phycfg()
16187 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; in tg3_10_100_only_device()
16639 val = tr32(MEMARB_MODE); in tg3_get_invariants()
16656 val = tr32(TG3_CPMU_STATUS); in tg3_get_invariants()
16734 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16826 val = tr32(GRC_MODE); in tg3_get_invariants()
16879 grc_misc_cfg = tr32(GRC_MISC_CFG); in tg3_get_invariants()
16981 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
17034 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) in tg3_get_device_address()
17073 hi = tr32(MAC_ADDR_0_HIGH); in tg3_get_device_address()
17074 lo = tr32(MAC_ADDR_0_LOW); in tg3_get_device_address()
17306 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17308 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); in tg3_do_test_dma()
17360 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); in tg3_test_dma()
17595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_bus_string()
17600 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == in tg3_bus_string()
17885 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { in tg3_init_one()
17946 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || in tg3_init_one()
17947 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { in tg3_init_one()