96 #define tg3_flag(tp, flag)				\  argument
97 	_tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
98 #define tg3_flag_set(tp, flag)				\  argument
99 	_tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
100 #define tg3_flag_clear(tp, flag)			\  argument
101 	_tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
136 #define TG3_MAX_MTU(tp)	\  argument
137 	(tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
143 #define TG3_RX_STD_RING_SIZE(tp) \  argument
144 	(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
147 #define TG3_RX_JMB_RING_SIZE(tp) \  argument
148 	(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
162 #define TG3_RX_STD_RING_BYTES(tp) \  argument
163 	(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
164 #define TG3_RX_JMB_RING_BYTES(tp) \  argument
165 	(sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
166 #define TG3_RX_RCB_RING_BYTES(tp) \  argument
167 	(sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
182 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \  argument
183 	(sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
185 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \  argument
186 	(sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
201 	#define TG3_RX_COPY_THRESH(tp)	TG3_RX_COPY_THRESHOLD  argument
203 	#define TG3_RX_COPY_THRESH(tp)	((tp)->rx_copy_thresh)  argument
207 #define TG3_RX_OFFSET(tp)	((tp)->rx_offset)  argument
209 #define TG3_RX_OFFSET(tp)	(NET_SKB_PAD)  argument
219 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)  argument
220 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)  argument
479 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)  in tg3_write32()  argument
481 	writel(val, tp->regs + off);  in tg3_write32()
484 static u32 tg3_read32(struct tg3 *tp, u32 off)  in tg3_read32()  argument
486 	return readl(tp->regs + off);  in tg3_read32()
489 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)  in tg3_ape_write32()  argument
491 	writel(val, tp->aperegs + off);  in tg3_ape_write32()
494 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)  in tg3_ape_read32()  argument
496 	return readl(tp->aperegs + off);  in tg3_ape_read32()
499 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)  in tg3_write_indirect_reg32()  argument
503 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_write_indirect_reg32()
504 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);  in tg3_write_indirect_reg32()
505 	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);  in tg3_write_indirect_reg32()
506 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_write_indirect_reg32()
509 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)  in tg3_write_flush_reg32()  argument
511 	writel(val, tp->regs + off);  in tg3_write_flush_reg32()
512 	readl(tp->regs + off);  in tg3_write_flush_reg32()
515 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)  in tg3_read_indirect_reg32()  argument
520 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_read_indirect_reg32()
521 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);  in tg3_read_indirect_reg32()
522 	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);  in tg3_read_indirect_reg32()
523 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_read_indirect_reg32()
527 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)  in tg3_write_indirect_mbox()  argument
532 		pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +  in tg3_write_indirect_mbox()
537 		pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +  in tg3_write_indirect_mbox()
542 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_write_indirect_mbox()
543 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);  in tg3_write_indirect_mbox()
544 	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);  in tg3_write_indirect_mbox()
545 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_write_indirect_mbox()
552 		pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,  in tg3_write_indirect_mbox()
553 				       tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);  in tg3_write_indirect_mbox()
557 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)  in tg3_read_indirect_mbox()  argument
562 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_read_indirect_mbox()
563 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);  in tg3_read_indirect_mbox()
564 	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);  in tg3_read_indirect_mbox()
565 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_read_indirect_mbox()
574 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)  in _tw32_flush()  argument
576 	if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))  in _tw32_flush()
578 		tp->write32(tp, off, val);  in _tw32_flush()
581 		tg3_write32(tp, off, val);  in _tw32_flush()
584 		tp->read32(tp, off);  in _tw32_flush()
593 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)  in tw32_mailbox_flush()  argument
595 	tp->write32_mbox(tp, off, val);  in tw32_mailbox_flush()
596 	if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||  in tw32_mailbox_flush()
597 	    (!tg3_flag(tp, MBOX_WRITE_REORDER) &&  in tw32_mailbox_flush()
598 	     !tg3_flag(tp, ICH_WORKAROUND)))  in tw32_mailbox_flush()
599 		tp->read32_mbox(tp, off);  in tw32_mailbox_flush()
602 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)  in tg3_write32_tx_mbox()  argument
604 	void __iomem *mbox = tp->regs + off;  in tg3_write32_tx_mbox()
606 	if (tg3_flag(tp, TXD_MBOX_HWBUG))  in tg3_write32_tx_mbox()
608 	if (tg3_flag(tp, MBOX_WRITE_REORDER) ||  in tg3_write32_tx_mbox()
609 	    tg3_flag(tp, FLUSH_POSTED_WRITES))  in tg3_write32_tx_mbox()
613 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)  in tg3_read32_mbox_5906()  argument
615 	return readl(tp->regs + off + GRCMBOX_BASE);  in tg3_read32_mbox_5906()
618 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)  in tg3_write32_mbox_5906()  argument
620 	writel(val, tp->regs + off + GRCMBOX_BASE);  in tg3_write32_mbox_5906()
623 #define tw32_mailbox(reg, val)		tp->write32_mbox(tp, reg, val)
624 #define tw32_mailbox_f(reg, val)	tw32_mailbox_flush(tp, (reg), (val))
625 #define tw32_rx_mbox(reg, val)		tp->write32_rx_mbox(tp, reg, val)
626 #define tw32_tx_mbox(reg, val)		tp->write32_tx_mbox(tp, reg, val)
627 #define tr32_mailbox(reg)		tp->read32_mbox(tp, reg)
629 #define tw32(reg, val)			tp->write32(tp, reg, val)
630 #define tw32_f(reg, val)		_tw32_flush(tp, (reg), (val), 0)
631 #define tw32_wait_f(reg, val, us)	_tw32_flush(tp, (reg), (val), (us))
632 #define tr32(reg)			tp->read32(tp, reg)
634 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)  in tg3_write_mem()  argument
638 	if (tg3_asic_rev(tp) == ASIC_REV_5906 &&  in tg3_write_mem()
642 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_write_mem()
643 	if (tg3_flag(tp, SRAM_USE_CONFIG)) {  in tg3_write_mem()
644 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);  in tg3_write_mem()
645 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_write_mem()
648 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_write_mem()
656 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_write_mem()
659 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)  in tg3_read_mem()  argument
663 	if (tg3_asic_rev(tp) == ASIC_REV_5906 &&  in tg3_read_mem()
669 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_read_mem()
670 	if (tg3_flag(tp, SRAM_USE_CONFIG)) {  in tg3_read_mem()
671 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);  in tg3_read_mem()
672 		pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_read_mem()
675 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_read_mem()
683 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_read_mem()
686 static void tg3_ape_lock_init(struct tg3 *tp)  in tg3_ape_lock_init()  argument
691 	if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_lock_init()
706 			if (!tp->pci_fn)  in tg3_ape_lock_init()
709 				bit = 1 << tp->pci_fn;  in tg3_ape_lock_init()
711 		tg3_ape_write32(tp, regbase + 4 * i, bit);  in tg3_ape_lock_init()
716 static int tg3_ape_lock(struct tg3 *tp, int locknum)  in tg3_ape_lock()  argument
722 	if (!tg3_flag(tp, ENABLE_APE))  in tg3_ape_lock()
727 		if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_lock()
732 		if (!tp->pci_fn)  in tg3_ape_lock()
735 			bit = 1 << tp->pci_fn;  in tg3_ape_lock()
747 	if (tg3_asic_rev(tp) == ASIC_REV_5761) {  in tg3_ape_lock()
757 	tg3_ape_write32(tp, req + off, bit);  in tg3_ape_lock()
761 		status = tg3_ape_read32(tp, gnt + off);  in tg3_ape_lock()
764 		if (pci_channel_offline(tp->pdev))  in tg3_ape_lock()
772 		tg3_ape_write32(tp, gnt + off, bit);  in tg3_ape_lock()
779 static void tg3_ape_unlock(struct tg3 *tp, int locknum)  in tg3_ape_unlock()  argument
783 	if (!tg3_flag(tp, ENABLE_APE))  in tg3_ape_unlock()
788 		if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_unlock()
793 		if (!tp->pci_fn)  in tg3_ape_unlock()
796 			bit = 1 << tp->pci_fn;  in tg3_ape_unlock()
808 	if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_unlock()
813 	tg3_ape_write32(tp, gnt + 4 * locknum, bit);  in tg3_ape_unlock()
816 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)  in tg3_ape_event_lock()  argument
821 		if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))  in tg3_ape_event_lock()
824 		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);  in tg3_ape_event_lock()
828 		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);  in tg3_ape_event_lock()
838 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)  in tg3_ape_wait_for_event()  argument
843 		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);  in tg3_ape_wait_for_event()
854 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,  in tg3_ape_scratchpad_read()  argument
860 	if (!tg3_flag(tp, APE_HAS_NCSI))  in tg3_ape_scratchpad_read()
863 	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);  in tg3_ape_scratchpad_read()
867 	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_ape_scratchpad_read()
871 	bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +  in tg3_ape_scratchpad_read()
874 	maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);  in tg3_ape_scratchpad_read()
883 		apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_ape_scratchpad_read()
888 		err = tg3_ape_event_lock(tp, 1000);  in tg3_ape_scratchpad_read()
895 		tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);  in tg3_ape_scratchpad_read()
897 		tg3_ape_write32(tp, bufoff, base_off);  in tg3_ape_scratchpad_read()
898 		tg3_ape_write32(tp, bufoff + sizeof(u32), length);  in tg3_ape_scratchpad_read()
900 		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);  in tg3_ape_scratchpad_read()
901 		tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);  in tg3_ape_scratchpad_read()
905 		if (tg3_ape_wait_for_event(tp, 30000))  in tg3_ape_scratchpad_read()
909 			u32 val = tg3_ape_read32(tp, msgoff + i);  in tg3_ape_scratchpad_read()
919 static int tg3_ape_send_event(struct tg3 *tp, u32 event)  in tg3_ape_send_event()  argument
924 	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);  in tg3_ape_send_event()
928 	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_ape_send_event()
933 	err = tg3_ape_event_lock(tp, 20000);  in tg3_ape_send_event()
937 	tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,  in tg3_ape_send_event()
940 	tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);  in tg3_ape_send_event()
941 	tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);  in tg3_ape_send_event()
946 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)  in tg3_ape_driver_state_change()  argument
951 	if (!tg3_flag(tp, ENABLE_APE))  in tg3_ape_driver_state_change()
956 		tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);  in tg3_ape_driver_state_change()
957 		tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,  in tg3_ape_driver_state_change()
959 		tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,  in tg3_ape_driver_state_change()
961 		apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);  in tg3_ape_driver_state_change()
962 		tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);  in tg3_ape_driver_state_change()
963 		tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,  in tg3_ape_driver_state_change()
965 		tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,  in tg3_ape_driver_state_change()
967 		tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,  in tg3_ape_driver_state_change()
973 		if (device_may_wakeup(&tp->pdev->dev) &&  in tg3_ape_driver_state_change()
974 		    tg3_flag(tp, WOL_ENABLE)) {  in tg3_ape_driver_state_change()
975 			tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,  in tg3_ape_driver_state_change()
981 		tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);  in tg3_ape_driver_state_change()
991 	tg3_ape_send_event(tp, event);  in tg3_ape_driver_state_change()
994 static void tg3_send_ape_heartbeat(struct tg3 *tp,  in tg3_send_ape_heartbeat()  argument
998 	if (!tg3_flag(tp, ENABLE_APE) ||  in tg3_send_ape_heartbeat()
999 	    time_before(jiffies, tp->ape_hb_jiffies + interval))  in tg3_send_ape_heartbeat()
1002 	tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);  in tg3_send_ape_heartbeat()
1003 	tp->ape_hb_jiffies = jiffies;  in tg3_send_ape_heartbeat()
1006 static void tg3_disable_ints(struct tg3 *tp)  in tg3_disable_ints()  argument
1011 	     (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));  in tg3_disable_ints()
1012 	for (i = 0; i < tp->irq_max; i++)  in tg3_disable_ints()
1013 		tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);  in tg3_disable_ints()
1016 static void tg3_enable_ints(struct tg3 *tp)  in tg3_enable_ints()  argument
1020 	tp->irq_sync = 0;  in tg3_enable_ints()
1024 	     (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));  in tg3_enable_ints()
1026 	tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;  in tg3_enable_ints()
1027 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_enable_ints()
1028 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_enable_ints()
1031 		if (tg3_flag(tp, 1SHOT_MSI))  in tg3_enable_ints()
1034 		tp->coal_now |= tnapi->coal_now;  in tg3_enable_ints()
1038 	if (!tg3_flag(tp, TAGGED_STATUS) &&  in tg3_enable_ints()
1039 	    (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))  in tg3_enable_ints()
1040 		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);  in tg3_enable_ints()
1042 		tw32(HOSTCC_MODE, tp->coal_now);  in tg3_enable_ints()
1044 	tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);  in tg3_enable_ints()
1049 	struct tg3 *tp = tnapi->tp;  in tg3_has_work()  local
1054 	if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {  in tg3_has_work()
1078 	struct tg3 *tp = tnapi->tp;  in tg3_int_reenable()  local
1087 	if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))  in tg3_int_reenable()
1088 		tw32(HOSTCC_MODE, tp->coalesce_mode |  in tg3_int_reenable()
1092 static void tg3_switch_clocks(struct tg3 *tp)  in tg3_switch_clocks()  argument
1097 	if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))  in tg3_switch_clocks()
1106 	tp->pci_clock_ctrl = clock_ctrl;  in tg3_switch_clocks()
1108 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_switch_clocks()
1127 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,  in __tg3_readphy()  argument
1134 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_readphy()
1136 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));  in __tg3_readphy()
1140 	tg3_ape_lock(tp, tp->phy_ape_lock);  in __tg3_readphy()
1171 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_readphy()
1172 		tw32_f(MAC_MI_MODE, tp->mi_mode);  in __tg3_readphy()
1176 	tg3_ape_unlock(tp, tp->phy_ape_lock);  in __tg3_readphy()
1181 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)  in tg3_readphy()  argument
1183 	return __tg3_readphy(tp, tp->phy_addr, reg, val);  in tg3_readphy()
1186 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,  in __tg3_writephy()  argument
1193 	if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&  in __tg3_writephy()
1197 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_writephy()
1199 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));  in __tg3_writephy()
1203 	tg3_ape_lock(tp, tp->phy_ape_lock);  in __tg3_writephy()
1230 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_writephy()
1231 		tw32_f(MAC_MI_MODE, tp->mi_mode);  in __tg3_writephy()
1235 	tg3_ape_unlock(tp, tp->phy_ape_lock);  in __tg3_writephy()
1240 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)  in tg3_writephy()  argument
1242 	return __tg3_writephy(tp, tp->phy_addr, reg, val);  in tg3_writephy()
1245 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)  in tg3_phy_cl45_write()  argument
1249 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);  in tg3_phy_cl45_write()
1253 	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);  in tg3_phy_cl45_write()
1257 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL,  in tg3_phy_cl45_write()
1262 	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);  in tg3_phy_cl45_write()
1268 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)  in tg3_phy_cl45_read()  argument
1272 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);  in tg3_phy_cl45_read()
1276 	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);  in tg3_phy_cl45_read()
1280 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL,  in tg3_phy_cl45_read()
1285 	err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);  in tg3_phy_cl45_read()
1291 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)  in tg3_phydsp_read()  argument
1295 	err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);  in tg3_phydsp_read()
1297 		err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);  in tg3_phydsp_read()
1302 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)  in tg3_phydsp_write()  argument
1306 	err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);  in tg3_phydsp_write()
1308 		err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);  in tg3_phydsp_write()
1313 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)  in tg3_phy_auxctl_read()  argument
1317 	err = tg3_writephy(tp, MII_TG3_AUX_CTRL,  in tg3_phy_auxctl_read()
1321 		err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);  in tg3_phy_auxctl_read()
1326 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)  in tg3_phy_auxctl_write()  argument
1331 	return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);  in tg3_phy_auxctl_write()
1334 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)  in tg3_phy_toggle_auxctl_smdsp()  argument
1339 	err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);  in tg3_phy_toggle_auxctl_smdsp()
1349 	err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,  in tg3_phy_toggle_auxctl_smdsp()
1355 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)  in tg3_phy_shdw_write()  argument
1357 	return tg3_writephy(tp, MII_TG3_MISC_SHDW,  in tg3_phy_shdw_write()
1361 static int tg3_bmcr_reset(struct tg3 *tp)  in tg3_bmcr_reset()  argument
1370 	err = tg3_writephy(tp, MII_BMCR, phy_control);  in tg3_bmcr_reset()
1376 		err = tg3_readphy(tp, MII_BMCR, &phy_control);  in tg3_bmcr_reset()
1394 	struct tg3 *tp = bp->priv;  in tg3_mdio_read()  local
1397 	spin_lock_bh(&tp->lock);  in tg3_mdio_read()
1399 	if (__tg3_readphy(tp, mii_id, reg, &val))  in tg3_mdio_read()
1402 	spin_unlock_bh(&tp->lock);  in tg3_mdio_read()
1409 	struct tg3 *tp = bp->priv;  in tg3_mdio_write()  local
1412 	spin_lock_bh(&tp->lock);  in tg3_mdio_write()
1414 	if (__tg3_writephy(tp, mii_id, reg, val))  in tg3_mdio_write()
1417 	spin_unlock_bh(&tp->lock);  in tg3_mdio_write()
1422 static void tg3_mdio_config_5785(struct tg3 *tp)  in tg3_mdio_config_5785()  argument
1427 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_mdio_config_5785()
1458 	if (!tg3_flag(tp, RGMII_INBAND_DISABLE))  in tg3_mdio_config_5785()
1471 	if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {  in tg3_mdio_config_5785()
1472 		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))  in tg3_mdio_config_5785()
1474 		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))  in tg3_mdio_config_5785()
1489 	if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {  in tg3_mdio_config_5785()
1490 		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))  in tg3_mdio_config_5785()
1495 		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))  in tg3_mdio_config_5785()
1503 static void tg3_mdio_start(struct tg3 *tp)  in tg3_mdio_start()  argument
1505 	tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;  in tg3_mdio_start()
1506 	tw32_f(MAC_MI_MODE, tp->mi_mode);  in tg3_mdio_start()
1509 	if (tg3_flag(tp, MDIOBUS_INITED) &&  in tg3_mdio_start()
1510 	    tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_mdio_start()
1511 		tg3_mdio_config_5785(tp);  in tg3_mdio_start()
1514 static int tg3_mdio_init(struct tg3 *tp)  in tg3_mdio_init()  argument
1520 	if (tg3_flag(tp, 5717_PLUS)) {  in tg3_mdio_init()
1523 		tp->phy_addr = tp->pci_fn + 1;  in tg3_mdio_init()
1525 		if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)  in tg3_mdio_init()
1531 			tp->phy_addr += 7;  in tg3_mdio_init()
1532 	} else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {  in tg3_mdio_init()
1535 		addr = ssb_gige_get_phyaddr(tp->pdev);  in tg3_mdio_init()
1538 		tp->phy_addr = addr;  in tg3_mdio_init()
1540 		tp->phy_addr = TG3_PHY_MII_ADDR;  in tg3_mdio_init()
1542 	tg3_mdio_start(tp);  in tg3_mdio_init()
1544 	if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))  in tg3_mdio_init()
1547 	tp->mdio_bus = mdiobus_alloc();  in tg3_mdio_init()
1548 	if (tp->mdio_bus == NULL)  in tg3_mdio_init()
1551 	tp->mdio_bus->name     = "tg3 mdio bus";  in tg3_mdio_init()
1552 	snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",  in tg3_mdio_init()
1553 		 (tp->pdev->bus->number << 8) | tp->pdev->devfn);  in tg3_mdio_init()
1554 	tp->mdio_bus->priv     = tp;  in tg3_mdio_init()
1555 	tp->mdio_bus->parent   = &tp->pdev->dev;  in tg3_mdio_init()
1556 	tp->mdio_bus->read     = &tg3_mdio_read;  in tg3_mdio_init()
1557 	tp->mdio_bus->write    = &tg3_mdio_write;  in tg3_mdio_init()
1558 	tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);  in tg3_mdio_init()
1565 	if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))  in tg3_mdio_init()
1566 		tg3_bmcr_reset(tp);  in tg3_mdio_init()
1568 	i = mdiobus_register(tp->mdio_bus);  in tg3_mdio_init()
1570 		dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);  in tg3_mdio_init()
1571 		mdiobus_free(tp->mdio_bus);  in tg3_mdio_init()
1575 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_mdio_init()
1578 		dev_warn(&tp->pdev->dev, "No PHY devices\n");  in tg3_mdio_init()
1579 		mdiobus_unregister(tp->mdio_bus);  in tg3_mdio_init()
1580 		mdiobus_free(tp->mdio_bus);  in tg3_mdio_init()
1595 		if (tg3_flag(tp, RGMII_INBAND_DISABLE))  in tg3_mdio_init()
1597 		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))  in tg3_mdio_init()
1599 		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))  in tg3_mdio_init()
1609 		tp->phy_flags |= TG3_PHYFLG_IS_FET;  in tg3_mdio_init()
1613 	tg3_flag_set(tp, MDIOBUS_INITED);  in tg3_mdio_init()
1615 	if (tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_mdio_init()
1616 		tg3_mdio_config_5785(tp);  in tg3_mdio_init()
1621 static void tg3_mdio_fini(struct tg3 *tp)  in tg3_mdio_fini()  argument
1623 	if (tg3_flag(tp, MDIOBUS_INITED)) {  in tg3_mdio_fini()
1624 		tg3_flag_clear(tp, MDIOBUS_INITED);  in tg3_mdio_fini()
1625 		mdiobus_unregister(tp->mdio_bus);  in tg3_mdio_fini()
1626 		mdiobus_free(tp->mdio_bus);  in tg3_mdio_fini()
1631 static inline void tg3_generate_fw_event(struct tg3 *tp)  in tg3_generate_fw_event()  argument
1639 	tp->last_event_jiffies = jiffies;  in tg3_generate_fw_event()
1645 static void tg3_wait_for_event_ack(struct tg3 *tp)  in tg3_wait_for_event_ack()  argument
1652 	time_remain = (long)(tp->last_event_jiffies + 1 +  in tg3_wait_for_event_ack()
1667 		if (pci_channel_offline(tp->pdev))  in tg3_wait_for_event_ack()
1675 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)  in tg3_phy_gather_ump_data()  argument
1680 	if (!tg3_readphy(tp, MII_BMCR, &reg))  in tg3_phy_gather_ump_data()
1682 	if (!tg3_readphy(tp, MII_BMSR, &reg))  in tg3_phy_gather_ump_data()
1687 	if (!tg3_readphy(tp, MII_ADVERTISE, &reg))  in tg3_phy_gather_ump_data()
1689 	if (!tg3_readphy(tp, MII_LPA, &reg))  in tg3_phy_gather_ump_data()
1694 	if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {  in tg3_phy_gather_ump_data()
1695 		if (!tg3_readphy(tp, MII_CTRL1000, &reg))  in tg3_phy_gather_ump_data()
1697 		if (!tg3_readphy(tp, MII_STAT1000, &reg))  in tg3_phy_gather_ump_data()
1702 	if (!tg3_readphy(tp, MII_PHYADDR, &reg))  in tg3_phy_gather_ump_data()
1710 static void tg3_ump_link_report(struct tg3 *tp)  in tg3_ump_link_report()  argument
1714 	if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))  in tg3_ump_link_report()
1717 	tg3_phy_gather_ump_data(tp, data);  in tg3_ump_link_report()
1719 	tg3_wait_for_event_ack(tp);  in tg3_ump_link_report()
1721 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);  in tg3_ump_link_report()
1722 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);  in tg3_ump_link_report()
1723 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);  in tg3_ump_link_report()
1724 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);  in tg3_ump_link_report()
1725 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);  in tg3_ump_link_report()
1726 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);  in tg3_ump_link_report()
1728 	tg3_generate_fw_event(tp);  in tg3_ump_link_report()
1732 static void tg3_stop_fw(struct tg3 *tp)  in tg3_stop_fw()  argument
1734 	if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {  in tg3_stop_fw()
1736 		tg3_wait_for_event_ack(tp);  in tg3_stop_fw()
1738 		tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);  in tg3_stop_fw()
1740 		tg3_generate_fw_event(tp);  in tg3_stop_fw()
1743 		tg3_wait_for_event_ack(tp);  in tg3_stop_fw()
1748 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)  in tg3_write_sig_pre_reset()  argument
1750 	tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,  in tg3_write_sig_pre_reset()
1753 	if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {  in tg3_write_sig_pre_reset()
1756 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_pre_reset()
1761 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_pre_reset()
1766 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_pre_reset()
1777 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)  in tg3_write_sig_post_reset()  argument
1779 	if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {  in tg3_write_sig_post_reset()
1782 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_post_reset()
1787 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_post_reset()
1798 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)  in tg3_write_sig_legacy()  argument
1800 	if (tg3_flag(tp, ENABLE_ASF)) {  in tg3_write_sig_legacy()
1803 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_legacy()
1808 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_legacy()
1813 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_legacy()
1823 static int tg3_poll_fw(struct tg3 *tp)  in tg3_poll_fw()  argument
1828 	if (tg3_flag(tp, NO_FWARE_REPORTED))  in tg3_poll_fw()
1831 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_poll_fw()
1836 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_poll_fw()
1841 			if (pci_channel_offline(tp->pdev))  in tg3_poll_fw()
1851 		tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);  in tg3_poll_fw()
1854 		if (pci_channel_offline(tp->pdev)) {  in tg3_poll_fw()
1855 			if (!tg3_flag(tp, NO_FWARE_REPORTED)) {  in tg3_poll_fw()
1856 				tg3_flag_set(tp, NO_FWARE_REPORTED);  in tg3_poll_fw()
1857 				netdev_info(tp->dev, "No firmware running\n");  in tg3_poll_fw()
1871 	if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {  in tg3_poll_fw()
1872 		tg3_flag_set(tp, NO_FWARE_REPORTED);  in tg3_poll_fw()
1874 		netdev_info(tp->dev, "No firmware running\n");  in tg3_poll_fw()
1877 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {  in tg3_poll_fw()
1887 static void tg3_link_report(struct tg3 *tp)  in tg3_link_report()  argument
1889 	if (!netif_carrier_ok(tp->dev)) {  in tg3_link_report()
1890 		netif_info(tp, link, tp->dev, "Link is down\n");  in tg3_link_report()
1891 		tg3_ump_link_report(tp);  in tg3_link_report()
1892 	} else if (netif_msg_link(tp)) {  in tg3_link_report()
1893 		netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",  in tg3_link_report()
1894 			    (tp->link_config.active_speed == SPEED_1000 ?  in tg3_link_report()
1896 			     (tp->link_config.active_speed == SPEED_100 ?  in tg3_link_report()
1898 			    (tp->link_config.active_duplex == DUPLEX_FULL ?  in tg3_link_report()
1901 		netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",  in tg3_link_report()
1902 			    (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?  in tg3_link_report()
1904 			    (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?  in tg3_link_report()
1907 		if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)  in tg3_link_report()
1908 			netdev_info(tp->dev, "EEE is %s\n",  in tg3_link_report()
1909 				    tp->setlpicnt ? "enabled" : "disabled");  in tg3_link_report()
1911 		tg3_ump_link_report(tp);  in tg3_link_report()
1914 	tp->link_up = netif_carrier_ok(tp->dev);  in tg3_link_report()
1977 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)  in tg3_setup_flow_control()  argument
1981 	u32 old_rx_mode = tp->rx_mode;  in tg3_setup_flow_control()
1982 	u32 old_tx_mode = tp->tx_mode;  in tg3_setup_flow_control()
1984 	if (tg3_flag(tp, USE_PHYLIB))  in tg3_setup_flow_control()
1985 		autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;  in tg3_setup_flow_control()
1987 		autoneg = tp->link_config.autoneg;  in tg3_setup_flow_control()
1989 	if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {  in tg3_setup_flow_control()
1990 		if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_setup_flow_control()
1995 		flowctrl = tp->link_config.flowctrl;  in tg3_setup_flow_control()
1997 	tp->link_config.active_flowctrl = flowctrl;  in tg3_setup_flow_control()
2000 		tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
2002 		tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
2004 	if (old_rx_mode != tp->rx_mode)  in tg3_setup_flow_control()
2005 		tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_setup_flow_control()
2008 		tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
2010 		tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
2012 	if (old_tx_mode != tp->tx_mode)  in tg3_setup_flow_control()
2013 		tw32_f(MAC_TX_MODE, tp->tx_mode);  in tg3_setup_flow_control()
2020 	struct tg3 *tp = netdev_priv(dev);  in tg3_adjust_link()  local
2021 	struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_adjust_link()
2023 	spin_lock_bh(&tp->lock);  in tg3_adjust_link()
2025 	mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |  in tg3_adjust_link()
2028 	oldflowctrl = tp->link_config.active_flowctrl;  in tg3_adjust_link()
2037 			 tg3_asic_rev(tp) != ASIC_REV_5785)  in tg3_adjust_link()
2046 				  tp->link_config.flowctrl);  in tg3_adjust_link()
2054 		tg3_setup_flow_control(tp, lcl_adv, rmt_adv);  in tg3_adjust_link()
2058 	if (mac_mode != tp->mac_mode) {  in tg3_adjust_link()
2059 		tp->mac_mode = mac_mode;  in tg3_adjust_link()
2060 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_adjust_link()
2064 	if (tg3_asic_rev(tp) == ASIC_REV_5785) {  in tg3_adjust_link()
2084 	if (phydev->link != tp->old_link ||  in tg3_adjust_link()
2085 	    phydev->speed != tp->link_config.active_speed ||  in tg3_adjust_link()
2086 	    phydev->duplex != tp->link_config.active_duplex ||  in tg3_adjust_link()
2087 	    oldflowctrl != tp->link_config.active_flowctrl)  in tg3_adjust_link()
2090 	tp->old_link = phydev->link;  in tg3_adjust_link()
2091 	tp->link_config.active_speed = phydev->speed;  in tg3_adjust_link()
2092 	tp->link_config.active_duplex = phydev->duplex;  in tg3_adjust_link()
2094 	spin_unlock_bh(&tp->lock);  in tg3_adjust_link()
2097 		tg3_link_report(tp);  in tg3_adjust_link()
2100 static int tg3_phy_init(struct tg3 *tp)  in tg3_phy_init()  argument
2104 	if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)  in tg3_phy_init()
2108 	tg3_bmcr_reset(tp);  in tg3_phy_init()
2110 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_phy_init()
2113 	phydev = phy_connect(tp->dev, phydev_name(phydev),  in tg3_phy_init()
2116 		dev_err(&tp->pdev->dev, "Could not attach to PHY\n");  in tg3_phy_init()
2124 		if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_init()
2137 		phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_phy_init()
2141 	tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;  in tg3_phy_init()
2150 static void tg3_phy_start(struct tg3 *tp)  in tg3_phy_start()  argument
2154 	if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_phy_start()
2157 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_phy_start()
2159 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {  in tg3_phy_start()
2160 		tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;  in tg3_phy_start()
2161 		phydev->speed = tp->link_config.speed;  in tg3_phy_start()
2162 		phydev->duplex = tp->link_config.duplex;  in tg3_phy_start()
2163 		phydev->autoneg = tp->link_config.autoneg;  in tg3_phy_start()
2164 		phydev->advertising = tp->link_config.advertising;  in tg3_phy_start()
2172 static void tg3_phy_stop(struct tg3 *tp)  in tg3_phy_stop()  argument
2174 	if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_phy_stop()
2177 	phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_phy_stop()
2180 static void tg3_phy_fini(struct tg3 *tp)  in tg3_phy_fini()  argument
2182 	if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {  in tg3_phy_fini()
2183 		phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_phy_fini()
2184 		tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;  in tg3_phy_fini()
2188 static int tg3_phy_set_extloopbk(struct tg3 *tp)  in tg3_phy_set_extloopbk()  argument
2193 	if (tp->phy_flags & TG3_PHYFLG_IS_FET)  in tg3_phy_set_extloopbk()
2196 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_phy_set_extloopbk()
2198 		err = tg3_phy_auxctl_write(tp,  in tg3_phy_set_extloopbk()
2205 	err = tg3_phy_auxctl_read(tp,  in tg3_phy_set_extloopbk()
2211 	err = tg3_phy_auxctl_write(tp,  in tg3_phy_set_extloopbk()
2218 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)  in tg3_phy_fet_toggle_apd()  argument
2222 	if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {  in tg3_phy_fet_toggle_apd()
2225 		tg3_writephy(tp, MII_TG3_FET_TEST,  in tg3_phy_fet_toggle_apd()
2227 		if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {  in tg3_phy_fet_toggle_apd()
2232 			tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);  in tg3_phy_fet_toggle_apd()
2234 		tg3_writephy(tp, MII_TG3_FET_TEST, phytest);  in tg3_phy_fet_toggle_apd()
2238 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)  in tg3_phy_toggle_apd()  argument
2242 	if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_phy_toggle_apd()
2243 	    (tg3_flag(tp, 5717_PLUS) &&  in tg3_phy_toggle_apd()
2244 	     (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))  in tg3_phy_toggle_apd()
2247 	if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_phy_toggle_apd()
2248 		tg3_phy_fet_toggle_apd(tp, enable);  in tg3_phy_toggle_apd()
2256 	if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)  in tg3_phy_toggle_apd()
2259 	tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);  in tg3_phy_toggle_apd()
2266 	tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);  in tg3_phy_toggle_apd()
2269 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)  in tg3_phy_toggle_automdix()  argument
2273 	if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_phy_toggle_automdix()
2274 	    (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_phy_toggle_automdix()
2277 	if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_phy_toggle_automdix()
2280 		if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {  in tg3_phy_toggle_automdix()
2283 			tg3_writephy(tp, MII_TG3_FET_TEST,  in tg3_phy_toggle_automdix()
2285 			if (!tg3_readphy(tp, reg, &phy)) {  in tg3_phy_toggle_automdix()
2290 				tg3_writephy(tp, reg, phy);  in tg3_phy_toggle_automdix()
2292 			tg3_writephy(tp, MII_TG3_FET_TEST, ephy);  in tg3_phy_toggle_automdix()
2297 		ret = tg3_phy_auxctl_read(tp,  in tg3_phy_toggle_automdix()
2304 			tg3_phy_auxctl_write(tp,  in tg3_phy_toggle_automdix()
2310 static void tg3_phy_set_wirespeed(struct tg3 *tp)  in tg3_phy_set_wirespeed()  argument
2315 	if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)  in tg3_phy_set_wirespeed()
2318 	ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);  in tg3_phy_set_wirespeed()
2320 		tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,  in tg3_phy_set_wirespeed()
2324 static void tg3_phy_apply_otp(struct tg3 *tp)  in tg3_phy_apply_otp()  argument
2328 	if (!tp->phy_otp)  in tg3_phy_apply_otp()
2331 	otp = tp->phy_otp;  in tg3_phy_apply_otp()
2333 	if (tg3_phy_toggle_auxctl_smdsp(tp, true))  in tg3_phy_apply_otp()
2338 	tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);  in tg3_phy_apply_otp()
2342 	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);  in tg3_phy_apply_otp()
2346 	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);  in tg3_phy_apply_otp()
2349 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);  in tg3_phy_apply_otp()
2352 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);  in tg3_phy_apply_otp()
2356 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);  in tg3_phy_apply_otp()
2358 	tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_apply_otp()
2361 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)  in tg3_eee_pull_config()  argument
2364 	struct ethtool_eee *dest = &tp->eee;  in tg3_eee_pull_config()
2366 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_eee_pull_config()
2372 	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))  in tg3_eee_pull_config()
2383 	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))  in tg3_eee_pull_config()
2388 	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))  in tg3_eee_pull_config()
2401 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)  in tg3_phy_eee_adjust()  argument
2405 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_phy_eee_adjust()
2408 	tp->setlpicnt = 0;  in tg3_phy_eee_adjust()
2410 	if (tp->link_config.autoneg == AUTONEG_ENABLE &&  in tg3_phy_eee_adjust()
2412 	    tp->link_config.active_duplex == DUPLEX_FULL &&  in tg3_phy_eee_adjust()
2413 	    (tp->link_config.active_speed == SPEED_100 ||  in tg3_phy_eee_adjust()
2414 	     tp->link_config.active_speed == SPEED_1000)) {  in tg3_phy_eee_adjust()
2417 		if (tp->link_config.active_speed == SPEED_1000)  in tg3_phy_eee_adjust()
2424 		tg3_eee_pull_config(tp, NULL);  in tg3_phy_eee_adjust()
2425 		if (tp->eee.eee_active)  in tg3_phy_eee_adjust()
2426 			tp->setlpicnt = 2;  in tg3_phy_eee_adjust()
2429 	if (!tp->setlpicnt) {  in tg3_phy_eee_adjust()
2431 		   !tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_eee_adjust()
2432 			tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);  in tg3_phy_eee_adjust()
2433 			tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_eee_adjust()
2441 static void tg3_phy_eee_enable(struct tg3 *tp)  in tg3_phy_eee_enable()  argument
2445 	if (tp->link_config.active_speed == SPEED_1000 &&  in tg3_phy_eee_enable()
2446 	    (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_phy_eee_enable()
2447 	     tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_phy_eee_enable()
2448 	     tg3_flag(tp, 57765_CLASS)) &&  in tg3_phy_eee_enable()
2449 	    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_eee_enable()
2452 		tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);  in tg3_phy_eee_enable()
2453 		tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_eee_enable()
2460 static int tg3_wait_macro_done(struct tg3 *tp)  in tg3_wait_macro_done()  argument
2467 		if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {  in tg3_wait_macro_done()
2478 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)  in tg3_phy_write_and_check_testpat()  argument
2491 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_phy_write_and_check_testpat()
2493 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);  in tg3_phy_write_and_check_testpat()
2496 			tg3_writephy(tp, MII_TG3_DSP_RW_PORT,  in tg3_phy_write_and_check_testpat()
2499 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);  in tg3_phy_write_and_check_testpat()
2500 		if (tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2505 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_phy_write_and_check_testpat()
2507 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);  in tg3_phy_write_and_check_testpat()
2508 		if (tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2513 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);  in tg3_phy_write_and_check_testpat()
2514 		if (tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2522 			if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||  in tg3_phy_write_and_check_testpat()
2523 			    tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||  in tg3_phy_write_and_check_testpat()
2524 			    tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2532 				tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);  in tg3_phy_write_and_check_testpat()
2533 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);  in tg3_phy_write_and_check_testpat()
2534 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);  in tg3_phy_write_and_check_testpat()
2544 static int tg3_phy_reset_chanpat(struct tg3 *tp)  in tg3_phy_reset_chanpat()  argument
2551 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_phy_reset_chanpat()
2553 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);  in tg3_phy_reset_chanpat()
2555 			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);  in tg3_phy_reset_chanpat()
2556 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);  in tg3_phy_reset_chanpat()
2557 		if (tg3_wait_macro_done(tp))  in tg3_phy_reset_chanpat()
2564 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)  in tg3_phy_reset_5703_4_5()  argument
2573 			err = tg3_bmcr_reset(tp);  in tg3_phy_reset_5703_4_5()
2580 		if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))  in tg3_phy_reset_5703_4_5()
2584 		tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);  in tg3_phy_reset_5703_4_5()
2587 		tg3_writephy(tp, MII_BMCR,  in tg3_phy_reset_5703_4_5()
2591 		if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))  in tg3_phy_reset_5703_4_5()
2594 		tg3_writephy(tp, MII_CTRL1000,  in tg3_phy_reset_5703_4_5()
2597 		err = tg3_phy_toggle_auxctl_smdsp(tp, true);  in tg3_phy_reset_5703_4_5()
2602 		tg3_phydsp_write(tp, 0x8005, 0x0800);  in tg3_phy_reset_5703_4_5()
2604 		err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);  in tg3_phy_reset_5703_4_5()
2609 	err = tg3_phy_reset_chanpat(tp);  in tg3_phy_reset_5703_4_5()
2613 	tg3_phydsp_write(tp, 0x8005, 0x0000);  in tg3_phy_reset_5703_4_5()
2615 	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);  in tg3_phy_reset_5703_4_5()
2616 	tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);  in tg3_phy_reset_5703_4_5()
2618 	tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset_5703_4_5()
2620 	tg3_writephy(tp, MII_CTRL1000, phy9_orig);  in tg3_phy_reset_5703_4_5()
2622 	err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);  in tg3_phy_reset_5703_4_5()
2627 	tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);  in tg3_phy_reset_5703_4_5()
2632 static void tg3_carrier_off(struct tg3 *tp)  in tg3_carrier_off()  argument
2634 	netif_carrier_off(tp->dev);  in tg3_carrier_off()
2635 	tp->link_up = false;  in tg3_carrier_off()
2638 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)  in tg3_warn_mgmt_link_flap()  argument
2640 	if (tg3_flag(tp, ENABLE_ASF))  in tg3_warn_mgmt_link_flap()
2641 		netdev_warn(tp->dev,  in tg3_warn_mgmt_link_flap()
2648 static int tg3_phy_reset(struct tg3 *tp)  in tg3_phy_reset()  argument
2653 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_phy_reset()
2658 	err  = tg3_readphy(tp, MII_BMSR, &val);  in tg3_phy_reset()
2659 	err |= tg3_readphy(tp, MII_BMSR, &val);  in tg3_phy_reset()
2663 	if (netif_running(tp->dev) && tp->link_up) {  in tg3_phy_reset()
2664 		netif_carrier_off(tp->dev);  in tg3_phy_reset()
2665 		tg3_link_report(tp);  in tg3_phy_reset()
2668 	if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_phy_reset()
2669 	    tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_phy_reset()
2670 	    tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_phy_reset()
2671 		err = tg3_phy_reset_5703_4_5(tp);  in tg3_phy_reset()
2678 	if (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_phy_reset()
2679 	    tg3_chip_rev(tp) != CHIPREV_5784_AX) {  in tg3_phy_reset()
2686 	err = tg3_bmcr_reset(tp);  in tg3_phy_reset()
2692 		tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);  in tg3_phy_reset()
2697 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||  in tg3_phy_reset()
2698 	    tg3_chip_rev(tp) == CHIPREV_5761_AX) {  in tg3_phy_reset()
2708 	if (tg3_flag(tp, 5717_PLUS) &&  in tg3_phy_reset()
2709 	    (tp->phy_flags & TG3_PHYFLG_MII_SERDES))  in tg3_phy_reset()
2712 	tg3_phy_apply_otp(tp);  in tg3_phy_reset()
2714 	if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)  in tg3_phy_reset()
2715 		tg3_phy_toggle_apd(tp, true);  in tg3_phy_reset()
2717 		tg3_phy_toggle_apd(tp, false);  in tg3_phy_reset()
2720 	if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&  in tg3_phy_reset()
2721 	    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_reset()
2722 		tg3_phydsp_write(tp, 0x201f, 0x2aaa);  in tg3_phy_reset()
2723 		tg3_phydsp_write(tp, 0x000a, 0x0323);  in tg3_phy_reset()
2724 		tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset()
2727 	if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {  in tg3_phy_reset()
2728 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);  in tg3_phy_reset()
2729 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);  in tg3_phy_reset()
2732 	if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {  in tg3_phy_reset()
2733 		if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_reset()
2734 			tg3_phydsp_write(tp, 0x000a, 0x310b);  in tg3_phy_reset()
2735 			tg3_phydsp_write(tp, 0x201f, 0x9506);  in tg3_phy_reset()
2736 			tg3_phydsp_write(tp, 0x401f, 0x14e2);  in tg3_phy_reset()
2737 			tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset()
2739 	} else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {  in tg3_phy_reset()
2740 		if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_reset()
2741 			tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);  in tg3_phy_reset()
2742 			if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {  in tg3_phy_reset()
2743 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);  in tg3_phy_reset()
2744 				tg3_writephy(tp, MII_TG3_TEST1,  in tg3_phy_reset()
2747 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);  in tg3_phy_reset()
2749 			tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset()
2755 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_phy_reset()
2757 		tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);  in tg3_phy_reset()
2758 	} else if (tg3_flag(tp, JUMBO_CAPABLE)) {  in tg3_phy_reset()
2760 		err = tg3_phy_auxctl_read(tp,  in tg3_phy_reset()
2763 			tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,  in tg3_phy_reset()
2770 	if (tg3_flag(tp, JUMBO_CAPABLE)) {  in tg3_phy_reset()
2771 		if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))  in tg3_phy_reset()
2772 			tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_phy_reset()
2776 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_phy_reset()
2778 		tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);  in tg3_phy_reset()
2781 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)  in tg3_phy_reset()
2782 		tg3_phydsp_write(tp, 0xffb, 0x4000);  in tg3_phy_reset()
2784 	tg3_phy_toggle_automdix(tp, true);  in tg3_phy_reset()
2785 	tg3_phy_set_wirespeed(tp);  in tg3_phy_reset()
2805 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)  in tg3_set_function_status()  argument
2809 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_set_function_status()
2810 	    tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_set_function_status()
2811 		status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);  in tg3_set_function_status()
2815 	shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;  in tg3_set_function_status()
2819 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_set_function_status()
2820 	    tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_set_function_status()
2821 		tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);  in tg3_set_function_status()
2828 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)  in tg3_pwrsrc_switch_to_vmain()  argument
2830 	if (!tg3_flag(tp, IS_NIC))  in tg3_pwrsrc_switch_to_vmain()
2833 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_pwrsrc_switch_to_vmain()
2834 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_pwrsrc_switch_to_vmain()
2835 	    tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_pwrsrc_switch_to_vmain()
2836 		if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))  in tg3_pwrsrc_switch_to_vmain()
2839 		tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);  in tg3_pwrsrc_switch_to_vmain()
2841 		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,  in tg3_pwrsrc_switch_to_vmain()
2844 		tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);  in tg3_pwrsrc_switch_to_vmain()
2846 		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,  in tg3_pwrsrc_switch_to_vmain()
2853 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)  in tg3_pwrsrc_die_with_vmain()  argument
2857 	if (!tg3_flag(tp, IS_NIC) ||  in tg3_pwrsrc_die_with_vmain()
2858 	    tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_pwrsrc_die_with_vmain()
2859 	    tg3_asic_rev(tp) == ASIC_REV_5701)  in tg3_pwrsrc_die_with_vmain()
2862 	grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;  in tg3_pwrsrc_die_with_vmain()
2877 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)  in tg3_pwrsrc_switch_to_vaux()  argument
2879 	if (!tg3_flag(tp, IS_NIC))  in tg3_pwrsrc_switch_to_vaux()
2882 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_pwrsrc_switch_to_vaux()
2883 	    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_pwrsrc_switch_to_vaux()
2884 		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |  in tg3_pwrsrc_switch_to_vaux()
2891 	} else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||  in tg3_pwrsrc_switch_to_vaux()
2892 		   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {  in tg3_pwrsrc_switch_to_vaux()
2899 				     tp->grc_local_ctrl;  in tg3_pwrsrc_switch_to_vaux()
2915 		if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_pwrsrc_switch_to_vaux()
2917 			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |  in tg3_pwrsrc_switch_to_vaux()
2923 		no_gpio2 = tp->nic_sram_data_cfg &  in tg3_pwrsrc_switch_to_vaux()
2936 			    tp->grc_local_ctrl | grc_local_ctrl,  in tg3_pwrsrc_switch_to_vaux()
2942 			    tp->grc_local_ctrl | grc_local_ctrl,  in tg3_pwrsrc_switch_to_vaux()
2948 				    tp->grc_local_ctrl | grc_local_ctrl,  in tg3_pwrsrc_switch_to_vaux()
2954 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)  in tg3_frob_aux_power_5717()  argument
2959 	if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))  in tg3_frob_aux_power_5717()
2962 	if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)  in tg3_frob_aux_power_5717()
2965 	msg = tg3_set_function_status(tp, msg);  in tg3_frob_aux_power_5717()
2971 		tg3_pwrsrc_switch_to_vaux(tp);  in tg3_frob_aux_power_5717()
2973 		tg3_pwrsrc_die_with_vmain(tp);  in tg3_frob_aux_power_5717()
2976 	tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);  in tg3_frob_aux_power_5717()
2979 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)  in tg3_frob_aux_power()  argument
2984 	if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))  in tg3_frob_aux_power()
2987 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_frob_aux_power()
2988 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_frob_aux_power()
2989 	    tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_frob_aux_power()
2990 		tg3_frob_aux_power_5717(tp, include_wol ?  in tg3_frob_aux_power()
2991 					tg3_flag(tp, WOL_ENABLE) != 0 : 0);  in tg3_frob_aux_power()
2995 	if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {  in tg3_frob_aux_power()
2998 		dev_peer = pci_get_drvdata(tp->pdev_peer);  in tg3_frob_aux_power()
3013 	if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||  in tg3_frob_aux_power()
3014 	    tg3_flag(tp, ENABLE_ASF))  in tg3_frob_aux_power()
3018 		tg3_pwrsrc_switch_to_vaux(tp);  in tg3_frob_aux_power()
3020 		tg3_pwrsrc_die_with_vmain(tp);  in tg3_frob_aux_power()
3023 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)  in tg3_5700_link_polarity()  argument
3025 	if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)  in tg3_5700_link_polarity()
3027 	else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {  in tg3_5700_link_polarity()
3036 static bool tg3_phy_power_bug(struct tg3 *tp)  in tg3_phy_power_bug()  argument
3038 	switch (tg3_asic_rev(tp)) {  in tg3_phy_power_bug()
3043 		if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_phy_power_bug()
3047 		if (!tp->pci_fn)  in tg3_phy_power_bug()
3052 		if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_phy_power_bug()
3053 		    !tp->pci_fn)  in tg3_phy_power_bug()
3061 static bool tg3_phy_led_bug(struct tg3 *tp)  in tg3_phy_led_bug()  argument
3063 	switch (tg3_asic_rev(tp)) {  in tg3_phy_led_bug()
3066 		if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_phy_led_bug()
3067 		    !tp->pci_fn)  in tg3_phy_led_bug()
3075 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)  in tg3_power_down_phy()  argument
3079 	if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)  in tg3_power_down_phy()
3082 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_power_down_phy()
3083 		if (tg3_asic_rev(tp) == ASIC_REV_5704) {  in tg3_power_down_phy()
3095 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_power_down_phy()
3096 		tg3_bmcr_reset(tp);  in tg3_power_down_phy()
3101 	} else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_power_down_phy()
3103 		if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {  in tg3_power_down_phy()
3106 			tg3_writephy(tp, MII_ADVERTISE, 0);  in tg3_power_down_phy()
3107 			tg3_writephy(tp, MII_BMCR,  in tg3_power_down_phy()
3110 			tg3_writephy(tp, MII_TG3_FET_TEST,  in tg3_power_down_phy()
3112 			if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {  in tg3_power_down_phy()
3114 				tg3_writephy(tp,  in tg3_power_down_phy()
3118 			tg3_writephy(tp, MII_TG3_FET_TEST, phytest);  in tg3_power_down_phy()
3122 		if (!tg3_phy_led_bug(tp))  in tg3_power_down_phy()
3123 			tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_power_down_phy()
3129 		tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);  in tg3_power_down_phy()
3135 	if (tg3_phy_power_bug(tp))  in tg3_power_down_phy()
3138 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||  in tg3_power_down_phy()
3139 	    tg3_chip_rev(tp) == CHIPREV_5761_AX) {  in tg3_power_down_phy()
3146 	tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);  in tg3_power_down_phy()
3150 static int tg3_nvram_lock(struct tg3 *tp)  in tg3_nvram_lock()  argument
3152 	if (tg3_flag(tp, NVRAM)) {  in tg3_nvram_lock()
3155 		if (tp->nvram_lock_cnt == 0) {  in tg3_nvram_lock()
3167 		tp->nvram_lock_cnt++;  in tg3_nvram_lock()
3173 static void tg3_nvram_unlock(struct tg3 *tp)  in tg3_nvram_unlock()  argument
3175 	if (tg3_flag(tp, NVRAM)) {  in tg3_nvram_unlock()
3176 		if (tp->nvram_lock_cnt > 0)  in tg3_nvram_unlock()
3177 			tp->nvram_lock_cnt--;  in tg3_nvram_unlock()
3178 		if (tp->nvram_lock_cnt == 0)  in tg3_nvram_unlock()
3184 static void tg3_enable_nvram_access(struct tg3 *tp)  in tg3_enable_nvram_access()  argument
3186 	if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {  in tg3_enable_nvram_access()
3194 static void tg3_disable_nvram_access(struct tg3 *tp)  in tg3_disable_nvram_access()  argument
3196 	if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {  in tg3_disable_nvram_access()
3203 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,  in tg3_nvram_read_using_eeprom()  argument
3245 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)  in tg3_nvram_exec_cmd()  argument
3264 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)  in tg3_nvram_phys_addr()  argument
3266 	if (tg3_flag(tp, NVRAM) &&  in tg3_nvram_phys_addr()
3267 	    tg3_flag(tp, NVRAM_BUFFERED) &&  in tg3_nvram_phys_addr()
3268 	    tg3_flag(tp, FLASH) &&  in tg3_nvram_phys_addr()
3269 	    !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&  in tg3_nvram_phys_addr()
3270 	    (tp->nvram_jedecnum == JEDEC_ATMEL))  in tg3_nvram_phys_addr()
3272 		addr = ((addr / tp->nvram_pagesize) <<  in tg3_nvram_phys_addr()
3274 		       (addr % tp->nvram_pagesize);  in tg3_nvram_phys_addr()
3279 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)  in tg3_nvram_logical_addr()  argument
3281 	if (tg3_flag(tp, NVRAM) &&  in tg3_nvram_logical_addr()
3282 	    tg3_flag(tp, NVRAM_BUFFERED) &&  in tg3_nvram_logical_addr()
3283 	    tg3_flag(tp, FLASH) &&  in tg3_nvram_logical_addr()
3284 	    !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&  in tg3_nvram_logical_addr()
3285 	    (tp->nvram_jedecnum == JEDEC_ATMEL))  in tg3_nvram_logical_addr()
3288 			tp->nvram_pagesize) +  in tg3_nvram_logical_addr()
3300 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)  in tg3_nvram_read()  argument
3304 	if (!tg3_flag(tp, NVRAM))  in tg3_nvram_read()
3305 		return tg3_nvram_read_using_eeprom(tp, offset, val);  in tg3_nvram_read()
3307 	offset = tg3_nvram_phys_addr(tp, offset);  in tg3_nvram_read()
3312 	ret = tg3_nvram_lock(tp);  in tg3_nvram_read()
3316 	tg3_enable_nvram_access(tp);  in tg3_nvram_read()
3319 	ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |  in tg3_nvram_read()
3325 	tg3_disable_nvram_access(tp);  in tg3_nvram_read()
3327 	tg3_nvram_unlock(tp);  in tg3_nvram_read()
3333 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)  in tg3_nvram_read_be32()  argument
3336 	int res = tg3_nvram_read(tp, offset, &v);  in tg3_nvram_read_be32()
3342 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,  in tg3_nvram_write_block_using_eeprom()  argument
3392 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,  in tg3_nvram_write_block_unbuffered()  argument
3396 	u32 pagesize = tp->nvram_pagesize;  in tg3_nvram_write_block_unbuffered()
3412 			ret = tg3_nvram_read_be32(tp, phy_addr + j,  in tg3_nvram_write_block_unbuffered()
3431 		tg3_enable_nvram_access(tp);  in tg3_nvram_write_block_unbuffered()
3439 		if (tg3_nvram_exec_cmd(tp, nvram_cmd))  in tg3_nvram_write_block_unbuffered()
3448 		if (tg3_nvram_exec_cmd(tp, nvram_cmd))  in tg3_nvram_write_block_unbuffered()
3454 		if (tg3_nvram_exec_cmd(tp, nvram_cmd))  in tg3_nvram_write_block_unbuffered()
3474 			ret = tg3_nvram_exec_cmd(tp, nvram_cmd);  in tg3_nvram_write_block_unbuffered()
3483 	tg3_nvram_exec_cmd(tp, nvram_cmd);  in tg3_nvram_write_block_unbuffered()
3491 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,  in tg3_nvram_write_block_buffered()  argument
3503 		page_off = offset % tp->nvram_pagesize;  in tg3_nvram_write_block_buffered()
3505 		phy_addr = tg3_nvram_phys_addr(tp, offset);  in tg3_nvram_write_block_buffered()
3511 		if (page_off == (tp->nvram_pagesize - 4))  in tg3_nvram_write_block_buffered()
3518 		    !tg3_flag(tp, FLASH) ||  in tg3_nvram_write_block_buffered()
3519 		    !tg3_flag(tp, 57765_PLUS))  in tg3_nvram_write_block_buffered()
3522 		if (tg3_asic_rev(tp) != ASIC_REV_5752 &&  in tg3_nvram_write_block_buffered()
3523 		    !tg3_flag(tp, 5755_PLUS) &&  in tg3_nvram_write_block_buffered()
3524 		    (tp->nvram_jedecnum == JEDEC_ST) &&  in tg3_nvram_write_block_buffered()
3529 			ret = tg3_nvram_exec_cmd(tp, cmd);  in tg3_nvram_write_block_buffered()
3533 		if (!tg3_flag(tp, FLASH)) {  in tg3_nvram_write_block_buffered()
3538 		ret = tg3_nvram_exec_cmd(tp, nvram_cmd);  in tg3_nvram_write_block_buffered()
3546 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)  in tg3_nvram_write_block()  argument
3550 	if (tg3_flag(tp, EEPROM_WRITE_PROT)) {  in tg3_nvram_write_block()
3551 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &  in tg3_nvram_write_block()
3556 	if (!tg3_flag(tp, NVRAM)) {  in tg3_nvram_write_block()
3557 		ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);  in tg3_nvram_write_block()
3561 		ret = tg3_nvram_lock(tp);  in tg3_nvram_write_block()
3565 		tg3_enable_nvram_access(tp);  in tg3_nvram_write_block()
3566 		if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))  in tg3_nvram_write_block()
3572 		if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {  in tg3_nvram_write_block()
3573 			ret = tg3_nvram_write_block_buffered(tp, offset, len,  in tg3_nvram_write_block()
3576 			ret = tg3_nvram_write_block_unbuffered(tp, offset, len,  in tg3_nvram_write_block()
3583 		tg3_disable_nvram_access(tp);  in tg3_nvram_write_block()
3584 		tg3_nvram_unlock(tp);  in tg3_nvram_write_block()
3587 	if (tg3_flag(tp, EEPROM_WRITE_PROT)) {  in tg3_nvram_write_block()
3588 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);  in tg3_nvram_write_block()
3601 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)  in tg3_pause_cpu()  argument
3611 		if (pci_channel_offline(tp->pdev))  in tg3_pause_cpu()
3619 static int tg3_rxcpu_pause(struct tg3 *tp)  in tg3_rxcpu_pause()  argument
3621 	int rc = tg3_pause_cpu(tp, RX_CPU_BASE);  in tg3_rxcpu_pause()
3631 static int tg3_txcpu_pause(struct tg3 *tp)  in tg3_txcpu_pause()  argument
3633 	return tg3_pause_cpu(tp, TX_CPU_BASE);  in tg3_txcpu_pause()
3637 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)  in tg3_resume_cpu()  argument
3644 static void tg3_rxcpu_resume(struct tg3 *tp)  in tg3_rxcpu_resume()  argument
3646 	tg3_resume_cpu(tp, RX_CPU_BASE);  in tg3_rxcpu_resume()
3650 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)  in tg3_halt_cpu()  argument
3654 	BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));  in tg3_halt_cpu()
3656 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_halt_cpu()
3663 		rc = tg3_rxcpu_pause(tp);  in tg3_halt_cpu()
3669 		if (tg3_flag(tp, IS_SSB_CORE))  in tg3_halt_cpu()
3672 		rc = tg3_txcpu_pause(tp);  in tg3_halt_cpu()
3676 		netdev_err(tp->dev, "%s timed out, %s CPU\n",  in tg3_halt_cpu()
3682 	if (tg3_flag(tp, NVRAM))  in tg3_halt_cpu()
3687 static int tg3_fw_data_len(struct tg3 *tp,  in tg3_fw_data_len()  argument
3706 	if (tp->fw_len == 0xffffffff)  in tg3_fw_data_len()
3709 		fw_len = tp->fw->size;  in tg3_fw_data_len()
3715 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,  in tg3_load_firmware_cpu()  argument
3721 	int total_len = tp->fw->size;  in tg3_load_firmware_cpu()
3723 	if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {  in tg3_load_firmware_cpu()
3724 		netdev_err(tp->dev,  in tg3_load_firmware_cpu()
3730 	if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)  in tg3_load_firmware_cpu()
3735 	if (tg3_asic_rev(tp) != ASIC_REV_57766) {  in tg3_load_firmware_cpu()
3739 		int lock_err = tg3_nvram_lock(tp);  in tg3_load_firmware_cpu()
3740 		err = tg3_halt_cpu(tp, cpu_base);  in tg3_load_firmware_cpu()
3742 			tg3_nvram_unlock(tp);  in tg3_load_firmware_cpu()
3747 			write_op(tp, cpu_scratch_base + i, 0);  in tg3_load_firmware_cpu()
3761 		for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)  in tg3_load_firmware_cpu()
3762 			write_op(tp, cpu_scratch_base +  in tg3_load_firmware_cpu()
3781 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)  in tg3_pause_cpu_and_set_pc()  argument
3802 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)  in tg3_load_5701_a0_firmware_fix()  argument
3807 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_load_5701_a0_firmware_fix()
3815 	err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,  in tg3_load_5701_a0_firmware_fix()
3821 	err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,  in tg3_load_5701_a0_firmware_fix()
3828 	err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,  in tg3_load_5701_a0_firmware_fix()
3831 		netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "  in tg3_load_5701_a0_firmware_fix()
3838 	tg3_rxcpu_resume(tp);  in tg3_load_5701_a0_firmware_fix()
3843 static int tg3_validate_rxcpu_state(struct tg3 *tp)  in tg3_validate_rxcpu_state()  argument
3860 		netdev_err(tp->dev, "Boot code not ready for service patches\n");  in tg3_validate_rxcpu_state()
3864 	val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);  in tg3_validate_rxcpu_state()
3866 		netdev_warn(tp->dev,  in tg3_validate_rxcpu_state()
3875 static void tg3_load_57766_firmware(struct tg3 *tp)  in tg3_load_57766_firmware()  argument
3879 	if (!tg3_flag(tp, NO_NVRAM))  in tg3_load_57766_firmware()
3882 	if (tg3_validate_rxcpu_state(tp))  in tg3_load_57766_firmware()
3885 	if (!tp->fw)  in tg3_load_57766_firmware()
3902 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_load_57766_firmware()
3906 	if (tg3_rxcpu_pause(tp))  in tg3_load_57766_firmware()
3910 	tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);  in tg3_load_57766_firmware()
3912 	tg3_rxcpu_resume(tp);  in tg3_load_57766_firmware()
3916 static int tg3_load_tso_firmware(struct tg3 *tp)  in tg3_load_tso_firmware()  argument
3922 	if (!tg3_flag(tp, FW_TSO))  in tg3_load_tso_firmware()
3925 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_load_tso_firmware()
3933 	cpu_scratch_size = tp->fw_len;  in tg3_load_tso_firmware()
3935 	if (tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_load_tso_firmware()
3944 	err = tg3_load_firmware_cpu(tp, cpu_base,  in tg3_load_tso_firmware()
3951 	err = tg3_pause_cpu_and_set_pc(tp, cpu_base,  in tg3_load_tso_firmware()
3954 		netdev_err(tp->dev,  in tg3_load_tso_firmware()
3961 	tg3_resume_cpu(tp, cpu_base);  in tg3_load_tso_firmware()
3966 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)  in __tg3_set_one_mac_addr()  argument
3985 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)  in __tg3_set_mac_addr()  argument
3993 		__tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);  in __tg3_set_mac_addr()
3996 	if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in __tg3_set_mac_addr()
3997 	    tg3_asic_rev(tp) == ASIC_REV_5704) {  in __tg3_set_mac_addr()
3999 			__tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);  in __tg3_set_mac_addr()
4002 	addr_high = (tp->dev->dev_addr[0] +  in __tg3_set_mac_addr()
4003 		     tp->dev->dev_addr[1] +  in __tg3_set_mac_addr()
4004 		     tp->dev->dev_addr[2] +  in __tg3_set_mac_addr()
4005 		     tp->dev->dev_addr[3] +  in __tg3_set_mac_addr()
4006 		     tp->dev->dev_addr[4] +  in __tg3_set_mac_addr()
4007 		     tp->dev->dev_addr[5]) &  in __tg3_set_mac_addr()
4012 static void tg3_enable_register_access(struct tg3 *tp)  in tg3_enable_register_access()  argument
4018 	pci_write_config_dword(tp->pdev,  in tg3_enable_register_access()
4019 			       TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);  in tg3_enable_register_access()
4022 static int tg3_power_up(struct tg3 *tp)  in tg3_power_up()  argument
4026 	tg3_enable_register_access(tp);  in tg3_power_up()
4028 	err = pci_set_power_state(tp->pdev, PCI_D0);  in tg3_power_up()
4031 		tg3_pwrsrc_switch_to_vmain(tp);  in tg3_power_up()
4033 		netdev_err(tp->dev, "Transition to D0 failed\n");  in tg3_power_up()
4041 static int tg3_power_down_prepare(struct tg3 *tp)  in tg3_power_down_prepare()  argument
4046 	tg3_enable_register_access(tp);  in tg3_power_down_prepare()
4049 	if (tg3_flag(tp, CLKREQ_BUG))  in tg3_power_down_prepare()
4050 		pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,  in tg3_power_down_prepare()
4057 	device_should_wake = device_may_wakeup(&tp->pdev->dev) &&  in tg3_power_down_prepare()
4058 			     tg3_flag(tp, WOL_ENABLE);  in tg3_power_down_prepare()
4060 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_power_down_prepare()
4062 		if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&  in tg3_power_down_prepare()
4063 		    !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {  in tg3_power_down_prepare()
4067 			phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_power_down_prepare()
4069 			tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;  in tg3_power_down_prepare()
4071 			tp->link_config.speed = phydev->speed;  in tg3_power_down_prepare()
4072 			tp->link_config.duplex = phydev->duplex;  in tg3_power_down_prepare()
4073 			tp->link_config.autoneg = phydev->autoneg;  in tg3_power_down_prepare()
4074 			tp->link_config.advertising = phydev->advertising;  in tg3_power_down_prepare()
4081 			if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {  in tg3_power_down_prepare()
4082 				if (tg3_flag(tp, WOL_SPEED_100MB))  in tg3_power_down_prepare()
4107 		if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))  in tg3_power_down_prepare()
4108 			tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;  in tg3_power_down_prepare()
4110 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_power_down_prepare()
4111 			tg3_setup_phy(tp, false);  in tg3_power_down_prepare()
4114 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_power_down_prepare()
4119 	} else if (!tg3_flag(tp, ENABLE_ASF)) {  in tg3_power_down_prepare()
4124 			tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);  in tg3_power_down_prepare()
4130 	if (tg3_flag(tp, WOL_CAP))  in tg3_power_down_prepare()
4131 		tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |  in tg3_power_down_prepare()
4139 		if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {  in tg3_power_down_prepare()
4141 			    !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {  in tg3_power_down_prepare()
4142 				tg3_phy_auxctl_write(tp,  in tg3_power_down_prepare()
4150 			if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_power_down_prepare()
4152 			else if (tp->phy_flags &  in tg3_power_down_prepare()
4154 				if (tp->link_config.active_speed == SPEED_1000)  in tg3_power_down_prepare()
4161 			mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;  in tg3_power_down_prepare()
4162 			if (tg3_asic_rev(tp) == ASIC_REV_5700) {  in tg3_power_down_prepare()
4163 				u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?  in tg3_power_down_prepare()
4165 				if (tg3_5700_link_polarity(tp, speed))  in tg3_power_down_prepare()
4174 		if (!tg3_flag(tp, 5750_PLUS))  in tg3_power_down_prepare()
4175 			tw32(MAC_LED_CTRL, tp->led_ctrl);  in tg3_power_down_prepare()
4178 		if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&  in tg3_power_down_prepare()
4179 		    (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))  in tg3_power_down_prepare()
4182 		if (tg3_flag(tp, ENABLE_APE))  in tg3_power_down_prepare()
4194 	if (!tg3_flag(tp, WOL_SPEED_100MB) &&  in tg3_power_down_prepare()
4195 	    (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_power_down_prepare()
4196 	     tg3_asic_rev(tp) == ASIC_REV_5701)) {  in tg3_power_down_prepare()
4199 		base_val = tp->pci_clock_ctrl;  in tg3_power_down_prepare()
4205 	} else if (tg3_flag(tp, 5780_CLASS) ||  in tg3_power_down_prepare()
4206 		   tg3_flag(tp, CPMU_PRESENT) ||  in tg3_power_down_prepare()
4207 		   tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_power_down_prepare()
4209 	} else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {  in tg3_power_down_prepare()
4212 		if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_power_down_prepare()
4213 		    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_power_down_prepare()
4218 		} else if (tg3_flag(tp, 5705_PLUS)) {  in tg3_power_down_prepare()
4226 		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,  in tg3_power_down_prepare()
4229 		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,  in tg3_power_down_prepare()
4232 		if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_power_down_prepare()
4235 			if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_power_down_prepare()
4236 			    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_power_down_prepare()
4245 				    tp->pci_clock_ctrl | newbits3, 40);  in tg3_power_down_prepare()
4249 	if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))  in tg3_power_down_prepare()
4250 		tg3_power_down_phy(tp, do_low_power);  in tg3_power_down_prepare()
4252 	tg3_frob_aux_power(tp, true);  in tg3_power_down_prepare()
4255 	if ((!tg3_flag(tp, IS_SSB_CORE)) &&  in tg3_power_down_prepare()
4256 	    ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||  in tg3_power_down_prepare()
4257 	     (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {  in tg3_power_down_prepare()
4262 		if (!tg3_flag(tp, ENABLE_ASF)) {  in tg3_power_down_prepare()
4265 			err = tg3_nvram_lock(tp);  in tg3_power_down_prepare()
4266 			tg3_halt_cpu(tp, RX_CPU_BASE);  in tg3_power_down_prepare()
4268 				tg3_nvram_unlock(tp);  in tg3_power_down_prepare()
4272 	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);  in tg3_power_down_prepare()
4274 	tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);  in tg3_power_down_prepare()
4279 static void tg3_power_down(struct tg3 *tp)  in tg3_power_down()  argument
4281 	pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));  in tg3_power_down()
4282 	pci_set_power_state(tp->pdev, PCI_D3hot);  in tg3_power_down()
4285 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)  in tg3_aux_stat_to_speed_duplex()  argument
4319 		if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_aux_stat_to_speed_duplex()
4332 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)  in tg3_phy_autoneg_cfg()  argument
4341 	err = tg3_writephy(tp, MII_ADVERTISE, new_adv);  in tg3_phy_autoneg_cfg()
4345 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_autoneg_cfg()
4348 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_phy_autoneg_cfg()
4349 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)  in tg3_phy_autoneg_cfg()
4352 		err = tg3_writephy(tp, MII_CTRL1000, new_adv);  in tg3_phy_autoneg_cfg()
4357 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_phy_autoneg_cfg()
4363 	err = tg3_phy_toggle_auxctl_smdsp(tp, true);  in tg3_phy_autoneg_cfg()
4375 		if (!tp->eee.eee_enabled) {  in tg3_phy_autoneg_cfg()
4377 			tp->eee.advertised = 0;  in tg3_phy_autoneg_cfg()
4379 			tp->eee.advertised = advertise &  in tg3_phy_autoneg_cfg()
4384 		err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);  in tg3_phy_autoneg_cfg()
4388 		switch (tg3_asic_rev(tp)) {  in tg3_phy_autoneg_cfg()
4398 			tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);  in tg3_phy_autoneg_cfg()
4402 			if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))  in tg3_phy_autoneg_cfg()
4403 				tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |  in tg3_phy_autoneg_cfg()
4407 		err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_autoneg_cfg()
4416 static void tg3_phy_copper_begin(struct tg3 *tp)  in tg3_phy_copper_begin()  argument
4418 	if (tp->link_config.autoneg == AUTONEG_ENABLE ||  in tg3_phy_copper_begin()
4419 	    (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {  in tg3_phy_copper_begin()
4422 		if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&  in tg3_phy_copper_begin()
4423 		    !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {  in tg3_phy_copper_begin()
4426 			if (tg3_flag(tp, WOL_SPEED_100MB))  in tg3_phy_copper_begin()
4429 			if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {  in tg3_phy_copper_begin()
4430 				if (!(tp->phy_flags &  in tg3_phy_copper_begin()
4438 			adv = tp->link_config.advertising;  in tg3_phy_copper_begin()
4439 			if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)  in tg3_phy_copper_begin()
4443 			fc = tp->link_config.flowctrl;  in tg3_phy_copper_begin()
4446 		tg3_phy_autoneg_cfg(tp, adv, fc);  in tg3_phy_copper_begin()
4448 		if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&  in tg3_phy_copper_begin()
4449 		    (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {  in tg3_phy_copper_begin()
4457 		tg3_writephy(tp, MII_BMCR,  in tg3_phy_copper_begin()
4463 		tp->link_config.active_speed = tp->link_config.speed;  in tg3_phy_copper_begin()
4464 		tp->link_config.active_duplex = tp->link_config.duplex;  in tg3_phy_copper_begin()
4466 		if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_phy_copper_begin()
4471 			tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);  in tg3_phy_copper_begin()
4475 		switch (tp->link_config.speed) {  in tg3_phy_copper_begin()
4489 		if (tp->link_config.duplex == DUPLEX_FULL)  in tg3_phy_copper_begin()
4492 		if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&  in tg3_phy_copper_begin()
4494 			tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);  in tg3_phy_copper_begin()
4499 				if (tg3_readphy(tp, MII_BMSR, &tmp) ||  in tg3_phy_copper_begin()
4500 				    tg3_readphy(tp, MII_BMSR, &tmp))  in tg3_phy_copper_begin()
4507 			tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_phy_copper_begin()
4513 static int tg3_phy_pull_config(struct tg3 *tp)  in tg3_phy_pull_config()  argument
4518 	err = tg3_readphy(tp, MII_BMCR, &val);  in tg3_phy_pull_config()
4523 		tp->link_config.autoneg = AUTONEG_DISABLE;  in tg3_phy_pull_config()
4524 		tp->link_config.advertising = 0;  in tg3_phy_pull_config()
4525 		tg3_flag_clear(tp, PAUSE_AUTONEG);  in tg3_phy_pull_config()
4531 			if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_phy_pull_config()
4534 			tp->link_config.speed = SPEED_10;  in tg3_phy_pull_config()
4537 			if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_phy_pull_config()
4540 			tp->link_config.speed = SPEED_100;  in tg3_phy_pull_config()
4543 			if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_pull_config()
4544 				tp->link_config.speed = SPEED_1000;  in tg3_phy_pull_config()
4553 			tp->link_config.duplex = DUPLEX_FULL;  in tg3_phy_pull_config()
4555 			tp->link_config.duplex = DUPLEX_HALF;  in tg3_phy_pull_config()
4557 		tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in tg3_phy_pull_config()
4563 	tp->link_config.autoneg = AUTONEG_ENABLE;  in tg3_phy_pull_config()
4564 	tp->link_config.advertising = ADVERTISED_Autoneg;  in tg3_phy_pull_config()
4565 	tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_phy_pull_config()
4567 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_phy_pull_config()
4570 		err = tg3_readphy(tp, MII_ADVERTISE, &val);  in tg3_phy_pull_config()
4575 		tp->link_config.advertising |= adv | ADVERTISED_TP;  in tg3_phy_pull_config()
4577 		tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);  in tg3_phy_pull_config()
4579 		tp->link_config.advertising |= ADVERTISED_FIBRE;  in tg3_phy_pull_config()
4582 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_pull_config()
4585 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_phy_pull_config()
4586 			err = tg3_readphy(tp, MII_CTRL1000, &val);  in tg3_phy_pull_config()
4592 			err = tg3_readphy(tp, MII_ADVERTISE, &val);  in tg3_phy_pull_config()
4597 			tp->link_config.flowctrl = adv;  in tg3_phy_pull_config()
4603 		tp->link_config.advertising |= adv;  in tg3_phy_pull_config()
4610 static int tg3_init_5401phy_dsp(struct tg3 *tp)  in tg3_init_5401phy_dsp()  argument
4616 	err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);  in tg3_init_5401phy_dsp()
4618 	err |= tg3_phydsp_write(tp, 0x0012, 0x1804);  in tg3_init_5401phy_dsp()
4619 	err |= tg3_phydsp_write(tp, 0x0013, 0x1204);  in tg3_init_5401phy_dsp()
4620 	err |= tg3_phydsp_write(tp, 0x8006, 0x0132);  in tg3_init_5401phy_dsp()
4621 	err |= tg3_phydsp_write(tp, 0x8006, 0x0232);  in tg3_init_5401phy_dsp()
4622 	err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);  in tg3_init_5401phy_dsp()
4629 static bool tg3_phy_eee_config_ok(struct tg3 *tp)  in tg3_phy_eee_config_ok()  argument
4633 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_phy_eee_config_ok()
4636 	tg3_eee_pull_config(tp, &eee);  in tg3_phy_eee_config_ok()
4638 	if (tp->eee.eee_enabled) {  in tg3_phy_eee_config_ok()
4639 		if (tp->eee.advertised != eee.advertised ||  in tg3_phy_eee_config_ok()
4640 		    tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||  in tg3_phy_eee_config_ok()
4641 		    tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)  in tg3_phy_eee_config_ok()
4652 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)  in tg3_phy_copper_an_config_ok()  argument
4656 	advertising = tp->link_config.advertising;  in tg3_phy_copper_an_config_ok()
4660 	if (tp->link_config.active_duplex == DUPLEX_FULL) {  in tg3_phy_copper_an_config_ok()
4661 		tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);  in tg3_phy_copper_an_config_ok()
4665 	if (tg3_readphy(tp, MII_ADVERTISE, lcladv))  in tg3_phy_copper_an_config_ok()
4671 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_copper_an_config_ok()
4676 		if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))  in tg3_phy_copper_an_config_ok()
4680 		    (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_phy_copper_an_config_ok()
4681 		     tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {  in tg3_phy_copper_an_config_ok()
4696 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)  in tg3_phy_copper_fetch_rmtadv()  argument
4700 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_copper_fetch_rmtadv()
4703 		if (tg3_readphy(tp, MII_STAT1000, &val))  in tg3_phy_copper_fetch_rmtadv()
4709 	if (tg3_readphy(tp, MII_LPA, rmtadv))  in tg3_phy_copper_fetch_rmtadv()
4713 	tp->link_config.rmt_adv = lpeth;  in tg3_phy_copper_fetch_rmtadv()
4718 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)  in tg3_test_and_report_link_chg()  argument
4720 	if (curr_link_up != tp->link_up) {  in tg3_test_and_report_link_chg()
4722 			netif_carrier_on(tp->dev);  in tg3_test_and_report_link_chg()
4724 			netif_carrier_off(tp->dev);  in tg3_test_and_report_link_chg()
4725 			if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_test_and_report_link_chg()
4726 				tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_test_and_report_link_chg()
4729 		tg3_link_report(tp);  in tg3_test_and_report_link_chg()
4736 static void tg3_clear_mac_status(struct tg3 *tp)  in tg3_clear_mac_status()  argument
4748 static void tg3_setup_eee(struct tg3 *tp)  in tg3_setup_eee()  argument
4754 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)  in tg3_setup_eee()
4763 	      (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |  in tg3_setup_eee()
4767 	if (tg3_asic_rev(tp) != ASIC_REV_5717)  in tg3_setup_eee()
4770 	if (tg3_flag(tp, ENABLE_APE))  in tg3_setup_eee()
4773 	tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);  in tg3_setup_eee()
4777 	       (tp->eee.tx_lpi_timer & 0xffff));  in tg3_setup_eee()
4784 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_copper_phy()  argument
4793 	tg3_clear_mac_status(tp);  in tg3_setup_copper_phy()
4795 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in tg3_setup_copper_phy()
4797 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));  in tg3_setup_copper_phy()
4801 	tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);  in tg3_setup_copper_phy()
4806 	if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_setup_copper_phy()
4807 	     tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_setup_copper_phy()
4808 	     tg3_asic_rev(tp) == ASIC_REV_5705) &&  in tg3_setup_copper_phy()
4809 	    tp->link_up) {  in tg3_setup_copper_phy()
4810 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4811 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_setup_copper_phy()
4816 		tg3_phy_reset(tp);  in tg3_setup_copper_phy()
4818 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_setup_copper_phy()
4819 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4820 		if (tg3_readphy(tp, MII_BMSR, &bmsr) ||  in tg3_setup_copper_phy()
4821 		    !tg3_flag(tp, INIT_COMPLETE))  in tg3_setup_copper_phy()
4825 			err = tg3_init_5401phy_dsp(tp);  in tg3_setup_copper_phy()
4829 			tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4832 				if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_setup_copper_phy()
4839 			if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==  in tg3_setup_copper_phy()
4842 			    tp->link_config.active_speed == SPEED_1000) {  in tg3_setup_copper_phy()
4843 				err = tg3_phy_reset(tp);  in tg3_setup_copper_phy()
4845 					err = tg3_init_5401phy_dsp(tp);  in tg3_setup_copper_phy()
4850 	} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_setup_copper_phy()
4851 		   tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {  in tg3_setup_copper_phy()
4853 		tg3_writephy(tp, 0x15, 0x0a75);  in tg3_setup_copper_phy()
4854 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);  in tg3_setup_copper_phy()
4855 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);  in tg3_setup_copper_phy()
4856 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);  in tg3_setup_copper_phy()
4860 	tg3_readphy(tp, MII_TG3_ISTAT, &val);  in tg3_setup_copper_phy()
4861 	tg3_readphy(tp, MII_TG3_ISTAT, &val);  in tg3_setup_copper_phy()
4863 	if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)  in tg3_setup_copper_phy()
4864 		tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);  in tg3_setup_copper_phy()
4865 	else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))  in tg3_setup_copper_phy()
4866 		tg3_writephy(tp, MII_TG3_IMASK, ~0);  in tg3_setup_copper_phy()
4868 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_setup_copper_phy()
4869 	    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_setup_copper_phy()
4870 		if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)  in tg3_setup_copper_phy()
4871 			tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_setup_copper_phy()
4874 			tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);  in tg3_setup_copper_phy()
4880 	tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;  in tg3_setup_copper_phy()
4881 	tp->link_config.rmt_adv = 0;  in tg3_setup_copper_phy()
4883 	if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {  in tg3_setup_copper_phy()
4884 		err = tg3_phy_auxctl_read(tp,  in tg3_setup_copper_phy()
4888 			tg3_phy_auxctl_write(tp,  in tg3_setup_copper_phy()
4897 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4898 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_setup_copper_phy()
4907 		tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);  in tg3_setup_copper_phy()
4910 			if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&  in tg3_setup_copper_phy()
4915 		tg3_aux_stat_to_speed_duplex(tp, aux_stat,  in tg3_setup_copper_phy()
4921 			tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_setup_copper_phy()
4922 			if (tg3_readphy(tp, MII_BMCR, &bmcr))  in tg3_setup_copper_phy()
4932 		tp->link_config.active_speed = current_speed;  in tg3_setup_copper_phy()
4933 		tp->link_config.active_duplex = current_duplex;  in tg3_setup_copper_phy()
4935 		if (tp->link_config.autoneg == AUTONEG_ENABLE) {  in tg3_setup_copper_phy()
4936 			bool eee_config_ok = tg3_phy_eee_config_ok(tp);  in tg3_setup_copper_phy()
4940 			    tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&  in tg3_setup_copper_phy()
4941 			    tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))  in tg3_setup_copper_phy()
4949 			    (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&  in tg3_setup_copper_phy()
4951 				tg3_setup_eee(tp);  in tg3_setup_copper_phy()
4952 				tg3_phy_reset(tp);  in tg3_setup_copper_phy()
4956 			    tp->link_config.speed == current_speed &&  in tg3_setup_copper_phy()
4957 			    tp->link_config.duplex == current_duplex) {  in tg3_setup_copper_phy()
4963 		    tp->link_config.active_duplex == DUPLEX_FULL) {  in tg3_setup_copper_phy()
4966 			if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_setup_copper_phy()
4974 			if (!tg3_readphy(tp, reg, &val) && (val & bit))  in tg3_setup_copper_phy()
4975 				tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;  in tg3_setup_copper_phy()
4977 			tg3_setup_flow_control(tp, lcl_adv, rmt_adv);  in tg3_setup_copper_phy()
4982 	if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {  in tg3_setup_copper_phy()
4983 		tg3_phy_copper_begin(tp);  in tg3_setup_copper_phy()
4985 		if (tg3_flag(tp, ROBOSWITCH)) {  in tg3_setup_copper_phy()
4990 			tp->link_config.active_speed = current_speed;  in tg3_setup_copper_phy()
4991 			tp->link_config.active_duplex = current_duplex;  in tg3_setup_copper_phy()
4994 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4995 		if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||  in tg3_setup_copper_phy()
4996 		    (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))  in tg3_setup_copper_phy()
5000 	tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;  in tg3_setup_copper_phy()
5002 		if (tp->link_config.active_speed == SPEED_100 ||  in tg3_setup_copper_phy()
5003 		    tp->link_config.active_speed == SPEED_10)  in tg3_setup_copper_phy()
5004 			tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_copper_phy()
5006 			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_copper_phy()
5007 	} else if (tp->phy_flags & TG3_PHYFLG_IS_FET)  in tg3_setup_copper_phy()
5008 		tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_copper_phy()
5010 		tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_copper_phy()
5015 	if (tg3_flag(tp, RGMII_MODE)) {  in tg3_setup_copper_phy()
5019 		if (tp->link_config.active_speed == SPEED_10)  in tg3_setup_copper_phy()
5021 		else if (tp->link_config.active_speed == SPEED_100)  in tg3_setup_copper_phy()
5024 		else if (tp->link_config.active_speed == SPEED_1000)  in tg3_setup_copper_phy()
5032 	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;  in tg3_setup_copper_phy()
5033 	if (tp->link_config.active_duplex == DUPLEX_HALF)  in tg3_setup_copper_phy()
5034 		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;  in tg3_setup_copper_phy()
5036 	if (tg3_asic_rev(tp) == ASIC_REV_5700) {  in tg3_setup_copper_phy()
5038 		    tg3_5700_link_polarity(tp, tp->link_config.active_speed))  in tg3_setup_copper_phy()
5039 			tp->mac_mode |= MAC_MODE_LINK_POLARITY;  in tg3_setup_copper_phy()
5041 			tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;  in tg3_setup_copper_phy()
5047 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&  in tg3_setup_copper_phy()
5048 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {  in tg3_setup_copper_phy()
5049 		tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;  in tg3_setup_copper_phy()
5050 		tw32_f(MAC_MI_MODE, tp->mi_mode);  in tg3_setup_copper_phy()
5054 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_copper_phy()
5057 	tg3_phy_eee_adjust(tp, current_link_up);  in tg3_setup_copper_phy()
5059 	if (tg3_flag(tp, USE_LINKCHG_REG)) {  in tg3_setup_copper_phy()
5067 	if (tg3_asic_rev(tp) == ASIC_REV_5700 &&  in tg3_setup_copper_phy()
5069 	    tp->link_config.active_speed == SPEED_1000 &&  in tg3_setup_copper_phy()
5070 	    (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {  in tg3_setup_copper_phy()
5076 		tg3_write_mem(tp,  in tg3_setup_copper_phy()
5082 	if (tg3_flag(tp, CLKREQ_BUG)) {  in tg3_setup_copper_phy()
5083 		if (tp->link_config.active_speed == SPEED_100 ||  in tg3_setup_copper_phy()
5084 		    tp->link_config.active_speed == SPEED_10)  in tg3_setup_copper_phy()
5085 			pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,  in tg3_setup_copper_phy()
5088 			pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,  in tg3_setup_copper_phy()
5092 	tg3_test_and_report_link_chg(tp, current_link_up);  in tg3_setup_copper_phy()
5161 static int tg3_fiber_aneg_smachine(struct tg3 *tp,  in tg3_fiber_aneg_smachine()  argument
5241 		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5242 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5264 		flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);  in tg3_fiber_aneg_smachine()
5270 		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5271 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5285 		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5286 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5371 		tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5372 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5413 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)  in fiber_autoneg()  argument
5423 	tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;  in fiber_autoneg()
5427 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);  in fiber_autoneg()
5436 		status = tg3_fiber_aneg_smachine(tp, &aninfo);  in fiber_autoneg()
5443 	tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;  in fiber_autoneg()
5444 	tw32_f(MAC_MODE, tp->mac_mode);  in fiber_autoneg()
5458 static void tg3_init_bcm8002(struct tg3 *tp)  in tg3_init_bcm8002()  argument
5464 	if (tg3_flag(tp, INIT_COMPLETE) &&  in tg3_init_bcm8002()
5469 	tg3_writephy(tp, 0x16, 0x8007);  in tg3_init_bcm8002()
5472 	tg3_writephy(tp, MII_BMCR, BMCR_RESET);  in tg3_init_bcm8002()
5480 	tg3_writephy(tp, 0x10, 0x8411);  in tg3_init_bcm8002()
5483 	tg3_writephy(tp, 0x11, 0x0a10);  in tg3_init_bcm8002()
5485 	tg3_writephy(tp, 0x18, 0x00a0);  in tg3_init_bcm8002()
5486 	tg3_writephy(tp, 0x16, 0x41ff);  in tg3_init_bcm8002()
5489 	tg3_writephy(tp, 0x13, 0x0400);  in tg3_init_bcm8002()
5491 	tg3_writephy(tp, 0x13, 0x0000);  in tg3_init_bcm8002()
5493 	tg3_writephy(tp, 0x11, 0x0a50);  in tg3_init_bcm8002()
5495 	tg3_writephy(tp, 0x11, 0x0a10);  in tg3_init_bcm8002()
5505 	tg3_writephy(tp, 0x10, 0x8011);  in tg3_init_bcm8002()
5508 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)  in tg3_setup_fiber_hw_autoneg()  argument
5522 	if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&  in tg3_setup_fiber_hw_autoneg()
5523 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {  in tg3_setup_fiber_hw_autoneg()
5535 	if (tp->link_config.autoneg != AUTONEG_ENABLE) {  in tg3_setup_fiber_hw_autoneg()
5550 			tg3_setup_flow_control(tp, 0, 0);  in tg3_setup_fiber_hw_autoneg()
5559 	flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);  in tg3_setup_fiber_hw_autoneg()
5566 		if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&  in tg3_setup_fiber_hw_autoneg()
5567 		    tp->serdes_counter &&  in tg3_setup_fiber_hw_autoneg()
5571 			tp->serdes_counter--;  in tg3_setup_fiber_hw_autoneg()
5582 		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;  in tg3_setup_fiber_hw_autoneg()
5583 		tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_hw_autoneg()
5603 			tp->link_config.rmt_adv =  in tg3_setup_fiber_hw_autoneg()
5606 			tg3_setup_flow_control(tp, local_adv, remote_adv);  in tg3_setup_fiber_hw_autoneg()
5608 			tp->serdes_counter = 0;  in tg3_setup_fiber_hw_autoneg()
5609 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_hw_autoneg()
5611 			if (tp->serdes_counter)  in tg3_setup_fiber_hw_autoneg()
5612 				tp->serdes_counter--;  in tg3_setup_fiber_hw_autoneg()
5634 					tg3_setup_flow_control(tp, 0, 0);  in tg3_setup_fiber_hw_autoneg()
5636 					tp->phy_flags |=  in tg3_setup_fiber_hw_autoneg()
5638 					tp->serdes_counter =  in tg3_setup_fiber_hw_autoneg()
5645 		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;  in tg3_setup_fiber_hw_autoneg()
5646 		tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_hw_autoneg()
5653 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)  in tg3_setup_fiber_by_hand()  argument
5660 	if (tp->link_config.autoneg == AUTONEG_ENABLE) {  in tg3_setup_fiber_by_hand()
5664 		if (fiber_autoneg(tp, &txflags, &rxflags)) {  in tg3_setup_fiber_by_hand()
5677 			tp->link_config.rmt_adv =  in tg3_setup_fiber_by_hand()
5680 			tg3_setup_flow_control(tp, local_adv, remote_adv);  in tg3_setup_fiber_by_hand()
5702 		tg3_setup_flow_control(tp, 0, 0);  in tg3_setup_fiber_by_hand()
5707 		tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));  in tg3_setup_fiber_by_hand()
5710 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_by_hand()
5718 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_fiber_phy()  argument
5727 	orig_pause_cfg = tp->link_config.active_flowctrl;  in tg3_setup_fiber_phy()
5728 	orig_active_speed = tp->link_config.active_speed;  in tg3_setup_fiber_phy()
5729 	orig_active_duplex = tp->link_config.active_duplex;  in tg3_setup_fiber_phy()
5731 	if (!tg3_flag(tp, HW_AUTONEG) &&  in tg3_setup_fiber_phy()
5732 	    tp->link_up &&  in tg3_setup_fiber_phy()
5733 	    tg3_flag(tp, INIT_COMPLETE)) {  in tg3_setup_fiber_phy()
5749 	tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);  in tg3_setup_fiber_phy()
5750 	tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;  in tg3_setup_fiber_phy()
5751 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_phy()
5754 	if (tp->phy_id == TG3_PHY_ID_BCM8002)  in tg3_setup_fiber_phy()
5755 		tg3_init_bcm8002(tp);  in tg3_setup_fiber_phy()
5762 	tp->link_config.rmt_adv = 0;  in tg3_setup_fiber_phy()
5765 	if (tg3_flag(tp, HW_AUTONEG))  in tg3_setup_fiber_phy()
5766 		current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);  in tg3_setup_fiber_phy()
5768 		current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);  in tg3_setup_fiber_phy()
5770 	tp->napi[0].hw_status->status =  in tg3_setup_fiber_phy()
5772 		 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));  in tg3_setup_fiber_phy()
5787 		if (tp->link_config.autoneg == AUTONEG_ENABLE &&  in tg3_setup_fiber_phy()
5788 		    tp->serdes_counter == 0) {  in tg3_setup_fiber_phy()
5789 			tw32_f(MAC_MODE, (tp->mac_mode |  in tg3_setup_fiber_phy()
5792 			tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_phy()
5797 		tp->link_config.active_speed = SPEED_1000;  in tg3_setup_fiber_phy()
5798 		tp->link_config.active_duplex = DUPLEX_FULL;  in tg3_setup_fiber_phy()
5799 		tw32(MAC_LED_CTRL, (tp->led_ctrl |  in tg3_setup_fiber_phy()
5803 		tp->link_config.active_speed = SPEED_UNKNOWN;  in tg3_setup_fiber_phy()
5804 		tp->link_config.active_duplex = DUPLEX_UNKNOWN;  in tg3_setup_fiber_phy()
5805 		tw32(MAC_LED_CTRL, (tp->led_ctrl |  in tg3_setup_fiber_phy()
5810 	if (!tg3_test_and_report_link_chg(tp, current_link_up)) {  in tg3_setup_fiber_phy()
5811 		u32 now_pause_cfg = tp->link_config.active_flowctrl;  in tg3_setup_fiber_phy()
5813 		    orig_active_speed != tp->link_config.active_speed ||  in tg3_setup_fiber_phy()
5814 		    orig_active_duplex != tp->link_config.active_duplex)  in tg3_setup_fiber_phy()
5815 			tg3_link_report(tp);  in tg3_setup_fiber_phy()
5821 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_fiber_mii_phy()  argument
5830 	if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_setup_fiber_mii_phy()
5831 	     tg3_asic_rev(tp) == ASIC_REV_5720) &&  in tg3_setup_fiber_mii_phy()
5832 	     !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&  in tg3_setup_fiber_mii_phy()
5836 			tg3_phy_reset(tp);  in tg3_setup_fiber_mii_phy()
5838 		tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;  in tg3_setup_fiber_mii_phy()
5841 			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_fiber_mii_phy()
5846 				tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_fiber_mii_phy()
5849 				tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_fiber_mii_phy()
5852 				tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_fiber_mii_phy()
5861 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_mii_phy()
5864 		tg3_clear_mac_status(tp);  in tg3_setup_fiber_mii_phy()
5869 	tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_fiber_mii_phy()
5870 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_mii_phy()
5873 	tg3_clear_mac_status(tp);  in tg3_setup_fiber_mii_phy()
5876 		tg3_phy_reset(tp);  in tg3_setup_fiber_mii_phy()
5878 	tp->link_config.rmt_adv = 0;  in tg3_setup_fiber_mii_phy()
5880 	err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5881 	err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5882 	if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_setup_fiber_mii_phy()
5889 	err |= tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_setup_fiber_mii_phy()
5891 	if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&  in tg3_setup_fiber_mii_phy()
5892 	    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {  in tg3_setup_fiber_mii_phy()
5894 	} else if (tp->link_config.autoneg == AUTONEG_ENABLE) {  in tg3_setup_fiber_mii_phy()
5897 		err |= tg3_readphy(tp, MII_ADVERTISE, &adv);  in tg3_setup_fiber_mii_phy()
5903 		newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);  in tg3_setup_fiber_mii_phy()
5904 		newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);  in tg3_setup_fiber_mii_phy()
5907 			tg3_writephy(tp, MII_ADVERTISE, newadv);  in tg3_setup_fiber_mii_phy()
5909 			tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_setup_fiber_mii_phy()
5912 			tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;  in tg3_setup_fiber_mii_phy()
5913 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_mii_phy()
5923 		if (tp->link_config.duplex == DUPLEX_FULL)  in tg3_setup_fiber_mii_phy()
5933 			if (tp->link_up) {  in tg3_setup_fiber_mii_phy()
5936 				err |= tg3_readphy(tp, MII_ADVERTISE, &adv);  in tg3_setup_fiber_mii_phy()
5940 				tg3_writephy(tp, MII_ADVERTISE, adv);  in tg3_setup_fiber_mii_phy()
5941 				tg3_writephy(tp, MII_BMCR, bmcr |  in tg3_setup_fiber_mii_phy()
5945 				tg3_carrier_off(tp);  in tg3_setup_fiber_mii_phy()
5947 			tg3_writephy(tp, MII_BMCR, new_bmcr);  in tg3_setup_fiber_mii_phy()
5949 			err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5950 			err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5951 			if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_setup_fiber_mii_phy()
5957 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_mii_phy()
5975 			err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);  in tg3_setup_fiber_mii_phy()
5976 			err |= tg3_readphy(tp, MII_LPA, &remote_adv);  in tg3_setup_fiber_mii_phy()
5985 				tp->link_config.rmt_adv =  in tg3_setup_fiber_mii_phy()
5987 			} else if (!tg3_flag(tp, 5780_CLASS)) {  in tg3_setup_fiber_mii_phy()
5997 		tg3_setup_flow_control(tp, local_adv, remote_adv);  in tg3_setup_fiber_mii_phy()
5999 	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;  in tg3_setup_fiber_mii_phy()
6000 	if (tp->link_config.active_duplex == DUPLEX_HALF)  in tg3_setup_fiber_mii_phy()
6001 		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;  in tg3_setup_fiber_mii_phy()
6003 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_mii_phy()
6008 	tp->link_config.active_speed = current_speed;  in tg3_setup_fiber_mii_phy()
6009 	tp->link_config.active_duplex = current_duplex;  in tg3_setup_fiber_mii_phy()
6011 	tg3_test_and_report_link_chg(tp, current_link_up);  in tg3_setup_fiber_mii_phy()
6015 static void tg3_serdes_parallel_detect(struct tg3 *tp)  in tg3_serdes_parallel_detect()  argument
6017 	if (tp->serdes_counter) {  in tg3_serdes_parallel_detect()
6019 		tp->serdes_counter--;  in tg3_serdes_parallel_detect()
6023 	if (!tp->link_up &&  in tg3_serdes_parallel_detect()
6024 	    (tp->link_config.autoneg == AUTONEG_ENABLE)) {  in tg3_serdes_parallel_detect()
6027 		tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_serdes_parallel_detect()
6032 			tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);  in tg3_serdes_parallel_detect()
6033 			tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);  in tg3_serdes_parallel_detect()
6036 			tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_serdes_parallel_detect()
6038 			tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);  in tg3_serdes_parallel_detect()
6039 			tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);  in tg3_serdes_parallel_detect()
6049 				tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_serdes_parallel_detect()
6050 				tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;  in tg3_serdes_parallel_detect()
6053 	} else if (tp->link_up &&  in tg3_serdes_parallel_detect()
6054 		   (tp->link_config.autoneg == AUTONEG_ENABLE) &&  in tg3_serdes_parallel_detect()
6055 		   (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {  in tg3_serdes_parallel_detect()
6059 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_serdes_parallel_detect()
6061 		tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);  in tg3_serdes_parallel_detect()
6066 			tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_serdes_parallel_detect()
6067 			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);  in tg3_serdes_parallel_detect()
6069 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_serdes_parallel_detect()
6075 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_phy()  argument
6080 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_setup_phy()
6081 		err = tg3_setup_fiber_phy(tp, force_reset);  in tg3_setup_phy()
6082 	else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_setup_phy()
6083 		err = tg3_setup_fiber_mii_phy(tp, force_reset);  in tg3_setup_phy()
6085 		err = tg3_setup_copper_phy(tp, force_reset);  in tg3_setup_phy()
6087 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {  in tg3_setup_phy()
6105 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_setup_phy()
6106 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_setup_phy()
6111 	if (tp->link_config.active_speed == SPEED_1000 &&  in tg3_setup_phy()
6112 	    tp->link_config.active_duplex == DUPLEX_HALF)  in tg3_setup_phy()
6119 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_setup_phy()
6120 		if (tp->link_up) {  in tg3_setup_phy()
6122 			     tp->coal.stats_block_coalesce_usecs);  in tg3_setup_phy()
6128 	if (tg3_flag(tp, ASPM_WORKAROUND)) {  in tg3_setup_phy()
6130 		if (!tp->link_up)  in tg3_setup_phy()
6132 			      tp->pwrmgmt_thresh;  in tg3_setup_phy()
6142 static u64 tg3_refclk_read(struct tg3 *tp)  in tg3_refclk_read()  argument
6149 static void tg3_refclk_write(struct tg3 *tp, u64 newval)  in tg3_refclk_write()  argument
6159 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6160 static inline void tg3_full_unlock(struct tg3 *tp);
6163 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_ts_info()  local
6169 	if (tg3_flag(tp, PTP_CAPABLE)) {  in tg3_get_ts_info()
6175 	if (tp->ptp_clock)  in tg3_get_ts_info()
6176 		info->phc_index = ptp_clock_index(tp->ptp_clock);  in tg3_get_ts_info()
6191 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_adjfreq()  local
6211 	tg3_full_lock(tp, 0);  in tg3_ptp_adjfreq()
6220 	tg3_full_unlock(tp);  in tg3_ptp_adjfreq()
6227 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_adjtime()  local
6229 	tg3_full_lock(tp, 0);  in tg3_ptp_adjtime()
6230 	tp->ptp_adjust += delta;  in tg3_ptp_adjtime()
6231 	tg3_full_unlock(tp);  in tg3_ptp_adjtime()
6239 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_gettime()  local
6241 	tg3_full_lock(tp, 0);  in tg3_ptp_gettime()
6242 	ns = tg3_refclk_read(tp);  in tg3_ptp_gettime()
6243 	ns += tp->ptp_adjust;  in tg3_ptp_gettime()
6244 	tg3_full_unlock(tp);  in tg3_ptp_gettime()
6255 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_settime()  local
6259 	tg3_full_lock(tp, 0);  in tg3_ptp_settime()
6260 	tg3_refclk_write(tp, ns);  in tg3_ptp_settime()
6261 	tp->ptp_adjust = 0;  in tg3_ptp_settime()
6262 	tg3_full_unlock(tp);  in tg3_ptp_settime()
6270 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_enable()  local
6279 		tg3_full_lock(tp, 0);  in tg3_ptp_enable()
6290 				netdev_warn(tp->dev,  in tg3_ptp_enable()
6297 				netdev_warn(tp->dev,  in tg3_ptp_enable()
6316 		tg3_full_unlock(tp);  in tg3_ptp_enable()
6342 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,  in tg3_hwclock_to_timestamp()  argument
6347 					   tp->ptp_adjust);  in tg3_hwclock_to_timestamp()
6351 static void tg3_ptp_init(struct tg3 *tp)  in tg3_ptp_init()  argument
6353 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_ptp_init()
6357 	tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));  in tg3_ptp_init()
6358 	tp->ptp_adjust = 0;  in tg3_ptp_init()
6359 	tp->ptp_info = tg3_ptp_caps;  in tg3_ptp_init()
6363 static void tg3_ptp_resume(struct tg3 *tp)  in tg3_ptp_resume()  argument
6365 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_ptp_resume()
6368 	tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);  in tg3_ptp_resume()
6369 	tp->ptp_adjust = 0;  in tg3_ptp_resume()
6372 static void tg3_ptp_fini(struct tg3 *tp)  in tg3_ptp_fini()  argument
6374 	if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)  in tg3_ptp_fini()
6377 	ptp_clock_unregister(tp->ptp_clock);  in tg3_ptp_fini()
6378 	tp->ptp_clock = NULL;  in tg3_ptp_fini()
6379 	tp->ptp_adjust = 0;  in tg3_ptp_fini()
6382 static inline int tg3_irq_sync(struct tg3 *tp)  in tg3_irq_sync()  argument
6384 	return tp->irq_sync;  in tg3_irq_sync()
6387 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)  in tg3_rd32_loop()  argument
6396 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)  in tg3_dump_legacy_regs()  argument
6398 	tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);  in tg3_dump_legacy_regs()
6399 	tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);  in tg3_dump_legacy_regs()
6400 	tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);  in tg3_dump_legacy_regs()
6401 	tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);  in tg3_dump_legacy_regs()
6402 	tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);  in tg3_dump_legacy_regs()
6403 	tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);  in tg3_dump_legacy_regs()
6404 	tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);  in tg3_dump_legacy_regs()
6405 	tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);  in tg3_dump_legacy_regs()
6406 	tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);  in tg3_dump_legacy_regs()
6407 	tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);  in tg3_dump_legacy_regs()
6408 	tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);  in tg3_dump_legacy_regs()
6409 	tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);  in tg3_dump_legacy_regs()
6410 	tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);  in tg3_dump_legacy_regs()
6411 	tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);  in tg3_dump_legacy_regs()
6412 	tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);  in tg3_dump_legacy_regs()
6413 	tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);  in tg3_dump_legacy_regs()
6414 	tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);  in tg3_dump_legacy_regs()
6415 	tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);  in tg3_dump_legacy_regs()
6416 	tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);  in tg3_dump_legacy_regs()
6418 	if (tg3_flag(tp, SUPPORT_MSIX))  in tg3_dump_legacy_regs()
6419 		tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);  in tg3_dump_legacy_regs()
6421 	tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);  in tg3_dump_legacy_regs()
6422 	tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);  in tg3_dump_legacy_regs()
6423 	tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);  in tg3_dump_legacy_regs()
6424 	tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);  in tg3_dump_legacy_regs()
6425 	tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);  in tg3_dump_legacy_regs()
6426 	tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);  in tg3_dump_legacy_regs()
6427 	tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);  in tg3_dump_legacy_regs()
6428 	tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);  in tg3_dump_legacy_regs()
6430 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_dump_legacy_regs()
6431 		tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);  in tg3_dump_legacy_regs()
6432 		tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);  in tg3_dump_legacy_regs()
6433 		tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);  in tg3_dump_legacy_regs()
6436 	tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);  in tg3_dump_legacy_regs()
6437 	tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);  in tg3_dump_legacy_regs()
6438 	tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);  in tg3_dump_legacy_regs()
6439 	tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);  in tg3_dump_legacy_regs()
6440 	tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);  in tg3_dump_legacy_regs()
6442 	if (tg3_flag(tp, NVRAM))  in tg3_dump_legacy_regs()
6443 		tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);  in tg3_dump_legacy_regs()
6446 static void tg3_dump_state(struct tg3 *tp)  in tg3_dump_state()  argument
6455 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_dump_state()
6460 		tg3_dump_legacy_regs(tp, regs);  in tg3_dump_state()
6467 		netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",  in tg3_dump_state()
6474 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_dump_state()
6475 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_dump_state()
6478 		netdev_err(tp->dev,  in tg3_dump_state()
6489 		netdev_err(tp->dev,  in tg3_dump_state()
6508 static void tg3_tx_recover(struct tg3 *tp)  in tg3_tx_recover()  argument
6510 	BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||  in tg3_tx_recover()
6511 	       tp->write32_tx_mbox == tg3_write_indirect_mbox);  in tg3_tx_recover()
6513 	netdev_warn(tp->dev,  in tg3_tx_recover()
6519 	tg3_flag_set(tp, TX_RECOVERY_PENDING);  in tg3_tx_recover()
6536 	struct tg3 *tp = tnapi->tp;  in tg3_tx()  local
6540 	int index = tnapi - tp->napi;  in tg3_tx()
6543 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_tx()
6546 	txq = netdev_get_tx_queue(tp->dev, index);  in tg3_tx()
6554 			tg3_tx_recover(tp);  in tg3_tx()
6563 			tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);  in tg3_tx()
6568 		pci_unmap_single(tp->pdev,  in tg3_tx()
6588 			pci_unmap_page(tp->pdev,  in tg3_tx()
6608 			tg3_tx_recover(tp);  in tg3_tx()
6642 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)  in tg3_rx_data_free()  argument
6644 	unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +  in tg3_rx_data_free()
6650 	pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),  in tg3_rx_data_free()
6668 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,  in tg3_alloc_rx_data()  argument
6680 		dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;  in tg3_alloc_rx_data()
6683 		data_size = tp->rx_pkt_map_sz;  in tg3_alloc_rx_data()
6687 		dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;  in tg3_alloc_rx_data()
6703 	skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +  in tg3_alloc_rx_data()
6715 	mapping = pci_map_single(tp->pdev,  in tg3_alloc_rx_data()
6716 				 data + TG3_RX_OFFSET(tp),  in tg3_alloc_rx_data()
6719 	if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {  in tg3_alloc_rx_data()
6742 	struct tg3 *tp = tnapi->tp;  in tg3_recycle_rx()  local
6745 	struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;  in tg3_recycle_rx()
6750 		dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;  in tg3_recycle_rx()
6758 		dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;  in tg3_recycle_rx()
6809 	struct tg3 *tp = tnapi->tp;  in tg3_rx()  local
6840 			ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];  in tg3_rx()
6846 			ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];  in tg3_rx()
6861 			tp->rx_dropped++;  in tg3_rx()
6865 		prefetch(data + TG3_RX_OFFSET(tp));  in tg3_rx()
6877 		if (len > TG3_RX_COPY_THRESH(tp)) {  in tg3_rx()
6881 			skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,  in tg3_rx()
6886 			pci_unmap_single(tp->pdev, dma_addr, skb_size,  in tg3_rx()
6901 			skb_reserve(skb, TG3_RX_OFFSET(tp));  in tg3_rx()
6906 			skb = netdev_alloc_skb(tp->dev,  in tg3_rx()
6912 			pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);  in tg3_rx()
6914 			       data + TG3_RX_OFFSET(tp),  in tg3_rx()
6916 			pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);  in tg3_rx()
6921 			tg3_hwclock_to_timestamp(tp, tstamp,  in tg3_rx()
6924 		if ((tp->dev->features & NETIF_F_RXCSUM) &&  in tg3_rx()
6932 		skb->protocol = eth_type_trans(skb, tp->dev);  in tg3_rx()
6934 		if (len > (tp->dev->mtu + ETH_HLEN) &&  in tg3_rx()
6942 		    !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))  in tg3_rx()
6954 		if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {  in tg3_rx()
6956 					       tp->rx_std_ring_mask;  in tg3_rx()
6964 		sw_idx &= tp->rx_ret_ring_mask;  in tg3_rx()
6978 	if (!tg3_flag(tp, ENABLE_RSS)) {  in tg3_rx()
6984 					       tp->rx_std_ring_mask;  in tg3_rx()
6990 					       tp->rx_jmb_ring_mask;  in tg3_rx()
7001 		tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;  in tg3_rx()
7002 		tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;  in tg3_rx()
7004 		if (tnapi != &tp->napi[1]) {  in tg3_rx()
7005 			tp->rx_refill = true;  in tg3_rx()
7006 			napi_schedule(&tp->napi[1].napi);  in tg3_rx()
7013 static void tg3_poll_link(struct tg3 *tp)  in tg3_poll_link()  argument
7016 	if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {  in tg3_poll_link()
7017 		struct tg3_hw_status *sblk = tp->napi[0].hw_status;  in tg3_poll_link()
7022 			spin_lock(&tp->lock);  in tg3_poll_link()
7023 			if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_poll_link()
7031 				tg3_setup_phy(tp, false);  in tg3_poll_link()
7032 			spin_unlock(&tp->lock);  in tg3_poll_link()
7037 static int tg3_rx_prodring_xfer(struct tg3 *tp,  in tg3_rx_prodring_xfer()  argument
7058 			cpycnt = tp->rx_std_ring_mask + 1 -  in tg3_rx_prodring_xfer()
7062 			     tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);  in tg3_rx_prodring_xfer()
7097 				       tp->rx_std_ring_mask;  in tg3_rx_prodring_xfer()
7099 				       tp->rx_std_ring_mask;  in tg3_rx_prodring_xfer()
7116 			cpycnt = tp->rx_jmb_ring_mask + 1 -  in tg3_rx_prodring_xfer()
7120 			     tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);  in tg3_rx_prodring_xfer()
7155 				       tp->rx_jmb_ring_mask;  in tg3_rx_prodring_xfer()
7157 				       tp->rx_jmb_ring_mask;  in tg3_rx_prodring_xfer()
7165 	struct tg3 *tp = tnapi->tp;  in tg3_poll_work()  local
7170 		if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))  in tg3_poll_work()
7184 	if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {  in tg3_poll_work()
7185 		struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;  in tg3_poll_work()
7190 		tp->rx_refill = false;  in tg3_poll_work()
7191 		for (i = 1; i <= tp->rxq_cnt; i++)  in tg3_poll_work()
7192 			err |= tg3_rx_prodring_xfer(tp, dpr,  in tg3_poll_work()
7193 						    &tp->napi[i].prodring);  in tg3_poll_work()
7208 			tw32_f(HOSTCC_MODE, tp->coal_now);  in tg3_poll_work()
7214 static inline void tg3_reset_task_schedule(struct tg3 *tp)  in tg3_reset_task_schedule()  argument
7216 	if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))  in tg3_reset_task_schedule()
7217 		schedule_work(&tp->reset_task);  in tg3_reset_task_schedule()
7220 static inline void tg3_reset_task_cancel(struct tg3 *tp)  in tg3_reset_task_cancel()  argument
7222 	cancel_work_sync(&tp->reset_task);  in tg3_reset_task_cancel()
7223 	tg3_flag_clear(tp, RESET_TASK_PENDING);  in tg3_reset_task_cancel()
7224 	tg3_flag_clear(tp, TX_RECOVERY_PENDING);  in tg3_reset_task_cancel()
7230 	struct tg3 *tp = tnapi->tp;  in tg3_poll_msix()  local
7237 		if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))  in tg3_poll_msix()
7258 			if (tnapi == &tp->napi[1] && tp->rx_refill)  in tg3_poll_msix()
7268 			if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {  in tg3_poll_msix()
7269 				tw32(HOSTCC_MODE, tp->coalesce_mode |  in tg3_poll_msix()
7278 	tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);  in tg3_poll_msix()
7284 	tg3_reset_task_schedule(tp);  in tg3_poll_msix()
7288 static void tg3_process_error(struct tg3 *tp)  in tg3_process_error()  argument
7293 	if (tg3_flag(tp, ERROR_PROCESSED))  in tg3_process_error()
7299 		netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");  in tg3_process_error()
7304 		netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");  in tg3_process_error()
7309 		netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");  in tg3_process_error()
7316 	tg3_dump_state(tp);  in tg3_process_error()
7318 	tg3_flag_set(tp, ERROR_PROCESSED);  in tg3_process_error()
7319 	tg3_reset_task_schedule(tp);  in tg3_process_error()
7325 	struct tg3 *tp = tnapi->tp;  in tg3_poll()  local
7331 			tg3_process_error(tp);  in tg3_poll()
7333 		tg3_poll_link(tp);  in tg3_poll()
7337 		if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))  in tg3_poll()
7343 		if (tg3_flag(tp, TAGGED_STATUS)) {  in tg3_poll()
7361 	tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);  in tg3_poll()
7367 	tg3_reset_task_schedule(tp);  in tg3_poll()
7371 static void tg3_napi_disable(struct tg3 *tp)  in tg3_napi_disable()  argument
7375 	for (i = tp->irq_cnt - 1; i >= 0; i--)  in tg3_napi_disable()
7376 		napi_disable(&tp->napi[i].napi);  in tg3_napi_disable()
7379 static void tg3_napi_enable(struct tg3 *tp)  in tg3_napi_enable()  argument
7383 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_napi_enable()
7384 		napi_enable(&tp->napi[i].napi);  in tg3_napi_enable()
7387 static void tg3_napi_init(struct tg3 *tp)  in tg3_napi_init()  argument
7391 	netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);  in tg3_napi_init()
7392 	for (i = 1; i < tp->irq_cnt; i++)  in tg3_napi_init()
7393 		netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);  in tg3_napi_init()
7396 static void tg3_napi_fini(struct tg3 *tp)  in tg3_napi_fini()  argument
7400 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_napi_fini()
7401 		netif_napi_del(&tp->napi[i].napi);  in tg3_napi_fini()
7404 static inline void tg3_netif_stop(struct tg3 *tp)  in tg3_netif_stop()  argument
7406 	netif_trans_update(tp->dev);	/* prevent tx timeout */  in tg3_netif_stop()
7407 	tg3_napi_disable(tp);  in tg3_netif_stop()
7408 	netif_carrier_off(tp->dev);  in tg3_netif_stop()
7409 	netif_tx_disable(tp->dev);  in tg3_netif_stop()
7413 static inline void tg3_netif_start(struct tg3 *tp)  in tg3_netif_start()  argument
7415 	tg3_ptp_resume(tp);  in tg3_netif_start()
7421 	netif_tx_wake_all_queues(tp->dev);  in tg3_netif_start()
7423 	if (tp->link_up)  in tg3_netif_start()
7424 		netif_carrier_on(tp->dev);  in tg3_netif_start()
7426 	tg3_napi_enable(tp);  in tg3_netif_start()
7427 	tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;  in tg3_netif_start()
7428 	tg3_enable_ints(tp);  in tg3_netif_start()
7431 static void tg3_irq_quiesce(struct tg3 *tp)  in tg3_irq_quiesce()  argument
7432 	__releases(tp->lock)  in tg3_irq_quiesce()
7433 	__acquires(tp->lock)  in tg3_irq_quiesce()
7437 	BUG_ON(tp->irq_sync);  in tg3_irq_quiesce()
7439 	tp->irq_sync = 1;  in tg3_irq_quiesce()
7442 	spin_unlock_bh(&tp->lock);  in tg3_irq_quiesce()
7444 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_irq_quiesce()
7445 		synchronize_irq(tp->napi[i].irq_vec);  in tg3_irq_quiesce()
7447 	spin_lock_bh(&tp->lock);  in tg3_irq_quiesce()
7455 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)  in tg3_full_lock()  argument
7457 	spin_lock_bh(&tp->lock);  in tg3_full_lock()
7459 		tg3_irq_quiesce(tp);  in tg3_full_lock()
7462 static inline void tg3_full_unlock(struct tg3 *tp)  in tg3_full_unlock()  argument
7464 	spin_unlock_bh(&tp->lock);  in tg3_full_unlock()
7473 	struct tg3 *tp = tnapi->tp;  in tg3_msi_1shot()  local
7479 	if (likely(!tg3_irq_sync(tp)))  in tg3_msi_1shot()
7492 	struct tg3 *tp = tnapi->tp;  in tg3_msi()  local
7505 	if (likely(!tg3_irq_sync(tp)))  in tg3_msi()
7514 	struct tg3 *tp = tnapi->tp;  in tg3_interrupt()  local
7524 		if (tg3_flag(tp, CHIP_RESETTING) ||  in tg3_interrupt()
7543 	if (tg3_irq_sync(tp))  in tg3_interrupt()
7563 	struct tg3 *tp = tnapi->tp;  in tg3_interrupt_tagged()  local
7573 		if (tg3_flag(tp, CHIP_RESETTING) ||  in tg3_interrupt_tagged()
7601 	if (tg3_irq_sync(tp))  in tg3_interrupt_tagged()
7616 	struct tg3 *tp = tnapi->tp;  in tg3_test_isr()  local
7621 		tg3_disable_ints(tp);  in tg3_test_isr()
7631 	struct tg3 *tp = netdev_priv(dev);  in tg3_poll_controller()  local
7633 	if (tg3_irq_sync(tp))  in tg3_poll_controller()
7636 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_poll_controller()
7637 		tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);  in tg3_poll_controller()
7643 	struct tg3 *tp = netdev_priv(dev);  in tg3_tx_timeout()  local
7645 	if (netif_msg_tx_err(tp)) {  in tg3_tx_timeout()
7647 		tg3_dump_state(tp);  in tg3_tx_timeout()
7650 	tg3_reset_task_schedule(tp);  in tg3_tx_timeout()
7664 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,  in tg3_4g_tso_overflow_test()  argument
7667 	if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {  in tg3_4g_tso_overflow_test()
7676 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,  in tg3_40bit_overflow_test()  argument
7680 	if (tg3_flag(tp, 40BIT_DMA_BUG))  in tg3_40bit_overflow_test()
7702 	struct tg3 *tp = tnapi->tp;  in tg3_tx_frag_set()  local
7705 	if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)  in tg3_tx_frag_set()
7711 	if (tg3_4g_tso_overflow_test(tp, map, len, mss))  in tg3_tx_frag_set()
7714 	if (tg3_40bit_overflow_test(tp, map, len))  in tg3_tx_frag_set()
7717 	if (tp->dma_limit) {  in tg3_tx_frag_set()
7720 		while (len > tp->dma_limit && *budget) {  in tg3_tx_frag_set()
7721 			u32 frag_len = tp->dma_limit;  in tg3_tx_frag_set()
7722 			len -= tp->dma_limit;  in tg3_tx_frag_set()
7726 				len += tp->dma_limit / 2;  in tg3_tx_frag_set()
7727 				frag_len = tp->dma_limit / 2;  in tg3_tx_frag_set()
7770 	pci_unmap_single(tnapi->tp->pdev,  in tg3_tx_skb_unmap()
7787 		pci_unmap_page(tnapi->tp->pdev,  in tg3_tx_skb_unmap()
7805 	struct tg3 *tp = tnapi->tp;  in tigon3_dma_hwbug_workaround()  local
7810 	if (tg3_asic_rev(tp) != ASIC_REV_5701)  in tigon3_dma_hwbug_workaround()
7824 		new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,  in tigon3_dma_hwbug_workaround()
7827 		if (pci_dma_mapping_error(tp->pdev, new_addr)) {  in tigon3_dma_hwbug_workaround()
7867 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,  in tg3_tso_bug()  argument
7889 	segs = skb_gso_segment(skb, tp->dev->features &  in tg3_tso_bug()
7898 		tg3_start_xmit(nskb, tp->dev);  in tg3_tso_bug()
7910 	struct tg3 *tp = netdev_priv(dev);  in tg3_start_xmit()  local
7924 	tnapi = &tp->napi[skb_get_queue_mapping(skb)];  in tg3_start_xmit()
7925 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_start_xmit()
7967 				return tg3_tso_bug(tp, tnapi, txq, skb);  in tg3_start_xmit()
7973 			    tg3_flag(tp, TSO_BUG)) {  in tg3_start_xmit()
7975 					return tg3_tso_bug(tp, tnapi, txq, skb);  in tg3_start_xmit()
7990 		if (tg3_flag(tp, HW_TSO_1) ||  in tg3_start_xmit()
7991 		    tg3_flag(tp, HW_TSO_2) ||  in tg3_start_xmit()
7992 		    tg3_flag(tp, HW_TSO_3)) {  in tg3_start_xmit()
8000 		if (tg3_flag(tp, HW_TSO_3)) {  in tg3_start_xmit()
8005 		} else if (tg3_flag(tp, HW_TSO_2))  in tg3_start_xmit()
8007 		else if (tg3_flag(tp, HW_TSO_1) ||  in tg3_start_xmit()
8008 			 tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_start_xmit()
8036 	if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&  in tg3_start_xmit()
8046 	    tg3_flag(tp, TX_TSTAMP_EN)) {  in tg3_start_xmit()
8053 	mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);  in tg3_start_xmit()
8054 	if (pci_dma_mapping_error(tp->pdev, mapping))  in tg3_start_xmit()
8063 	if (tg3_flag(tp, 5701_DMA_BUG))  in tg3_start_xmit()
8073 		if (!tg3_flag(tp, HW_TSO_1) &&  in tg3_start_xmit()
8074 		    !tg3_flag(tp, HW_TSO_2) &&  in tg3_start_xmit()
8075 		    !tg3_flag(tp, HW_TSO_3))  in tg3_start_xmit()
8086 			mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,  in tg3_start_xmit()
8092 			if (dma_mapping_error(&tp->pdev->dev, mapping))  in tg3_start_xmit()
8118 			return tg3_tso_bug(tp, tnapi, txq, skb);  in tg3_start_xmit()
8165 	tp->tx_dropped++;  in tg3_start_xmit()
8169 static void tg3_mac_loopback(struct tg3 *tp, bool enable)  in tg3_mac_loopback()  argument
8172 		tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |  in tg3_mac_loopback()
8175 		tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;  in tg3_mac_loopback()
8177 		if (!tg3_flag(tp, 5705_PLUS))  in tg3_mac_loopback()
8178 			tp->mac_mode |= MAC_MODE_LINK_POLARITY;  in tg3_mac_loopback()
8180 		if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)  in tg3_mac_loopback()
8181 			tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_mac_loopback()
8183 			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_mac_loopback()
8185 		tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;  in tg3_mac_loopback()
8187 		if (tg3_flag(tp, 5705_PLUS) ||  in tg3_mac_loopback()
8188 		    (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||  in tg3_mac_loopback()
8189 		    tg3_asic_rev(tp) == ASIC_REV_5700)  in tg3_mac_loopback()
8190 			tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;  in tg3_mac_loopback()
8193 	tw32(MAC_MODE, tp->mac_mode);  in tg3_mac_loopback()
8197 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)  in tg3_phy_lpbk_set()  argument
8201 	tg3_phy_toggle_apd(tp, false);  in tg3_phy_lpbk_set()
8202 	tg3_phy_toggle_automdix(tp, false);  in tg3_phy_lpbk_set()
8204 	if (extlpbk && tg3_phy_set_extloopbk(tp))  in tg3_phy_lpbk_set()
8216 		if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_phy_lpbk_set()
8226 		if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {  in tg3_phy_lpbk_set()
8227 			tg3_readphy(tp, MII_CTRL1000, &val);  in tg3_phy_lpbk_set()
8230 			tg3_writephy(tp, MII_CTRL1000, val);  in tg3_phy_lpbk_set()
8234 			tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);  in tg3_phy_lpbk_set()
8239 	tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_phy_lpbk_set()
8242 	if (tp->phy_flags & TG3_PHYFLG_IS_FET)  in tg3_phy_lpbk_set()
8243 		tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_phy_lpbk_set()
8247 	if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&  in tg3_phy_lpbk_set()
8248 	    tg3_asic_rev(tp) == ASIC_REV_5785) {  in tg3_phy_lpbk_set()
8249 		tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |  in tg3_phy_lpbk_set()
8254 		tg3_readphy(tp, MII_TG3_FET_PTEST, &val);  in tg3_phy_lpbk_set()
8258 	if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_phy_lpbk_set()
8259 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_phy_lpbk_set()
8262 		tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_phy_lpbk_set()
8265 	mac_mode = tp->mac_mode &  in tg3_phy_lpbk_set()
8272 	if (tg3_asic_rev(tp) == ASIC_REV_5700) {  in tg3_phy_lpbk_set()
8273 		u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;  in tg3_phy_lpbk_set()
8280 		tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_phy_lpbk_set()
8292 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_loopback()  local
8295 		if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)  in tg3_set_loopback()
8298 		spin_lock_bh(&tp->lock);  in tg3_set_loopback()
8299 		tg3_mac_loopback(tp, true);  in tg3_set_loopback()
8300 		netif_carrier_on(tp->dev);  in tg3_set_loopback()
8301 		spin_unlock_bh(&tp->lock);  in tg3_set_loopback()
8304 		if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))  in tg3_set_loopback()
8307 		spin_lock_bh(&tp->lock);  in tg3_set_loopback()
8308 		tg3_mac_loopback(tp, false);  in tg3_set_loopback()
8310 		tg3_setup_phy(tp, true);  in tg3_set_loopback()
8311 		spin_unlock_bh(&tp->lock);  in tg3_set_loopback()
8319 	struct tg3 *tp = netdev_priv(dev);  in tg3_fix_features()  local
8321 	if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))  in tg3_fix_features()
8337 static void tg3_rx_prodring_free(struct tg3 *tp,  in tg3_rx_prodring_free()  argument
8342 	if (tpr != &tp->napi[0].prodring) {  in tg3_rx_prodring_free()
8344 		     i = (i + 1) & tp->rx_std_ring_mask)  in tg3_rx_prodring_free()
8345 			tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],  in tg3_rx_prodring_free()
8346 					tp->rx_pkt_map_sz);  in tg3_rx_prodring_free()
8348 		if (tg3_flag(tp, JUMBO_CAPABLE)) {  in tg3_rx_prodring_free()
8351 			     i = (i + 1) & tp->rx_jmb_ring_mask) {  in tg3_rx_prodring_free()
8352 				tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],  in tg3_rx_prodring_free()
8360 	for (i = 0; i <= tp->rx_std_ring_mask; i++)  in tg3_rx_prodring_free()
8361 		tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],  in tg3_rx_prodring_free()
8362 				tp->rx_pkt_map_sz);  in tg3_rx_prodring_free()
8364 	if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {  in tg3_rx_prodring_free()
8365 		for (i = 0; i <= tp->rx_jmb_ring_mask; i++)  in tg3_rx_prodring_free()
8366 			tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],  in tg3_rx_prodring_free()
8378 static int tg3_rx_prodring_alloc(struct tg3 *tp,  in tg3_rx_prodring_alloc()  argument
8388 	if (tpr != &tp->napi[0].prodring) {  in tg3_rx_prodring_alloc()
8390 		       TG3_RX_STD_BUFF_RING_SIZE(tp));  in tg3_rx_prodring_alloc()
8393 			       TG3_RX_JMB_BUFF_RING_SIZE(tp));  in tg3_rx_prodring_alloc()
8398 	memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));  in tg3_rx_prodring_alloc()
8401 	if (tg3_flag(tp, 5780_CLASS) &&  in tg3_rx_prodring_alloc()
8402 	    tp->dev->mtu > ETH_DATA_LEN)  in tg3_rx_prodring_alloc()
8404 	tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);  in tg3_rx_prodring_alloc()
8410 	for (i = 0; i <= tp->rx_std_ring_mask; i++) {  in tg3_rx_prodring_alloc()
8421 	for (i = 0; i < tp->rx_pending; i++) {  in tg3_rx_prodring_alloc()
8424 		if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,  in tg3_rx_prodring_alloc()
8426 			netdev_warn(tp->dev,  in tg3_rx_prodring_alloc()
8429 				    "successfully\n", i, tp->rx_pending);  in tg3_rx_prodring_alloc()
8432 			tp->rx_pending = i;  in tg3_rx_prodring_alloc()
8437 	if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))  in tg3_rx_prodring_alloc()
8440 	memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));  in tg3_rx_prodring_alloc()
8442 	if (!tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_rx_prodring_alloc()
8445 	for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {  in tg3_rx_prodring_alloc()
8456 	for (i = 0; i < tp->rx_jumbo_pending; i++) {  in tg3_rx_prodring_alloc()
8459 		if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,  in tg3_rx_prodring_alloc()
8461 			netdev_warn(tp->dev,  in tg3_rx_prodring_alloc()
8464 				    "successfully\n", i, tp->rx_jumbo_pending);  in tg3_rx_prodring_alloc()
8467 			tp->rx_jumbo_pending = i;  in tg3_rx_prodring_alloc()
8476 	tg3_rx_prodring_free(tp, tpr);  in tg3_rx_prodring_alloc()
8480 static void tg3_rx_prodring_fini(struct tg3 *tp,  in tg3_rx_prodring_fini()  argument
8488 		dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),  in tg3_rx_prodring_fini()
8493 		dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),  in tg3_rx_prodring_fini()
8499 static int tg3_rx_prodring_init(struct tg3 *tp,  in tg3_rx_prodring_init()  argument
8502 	tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),  in tg3_rx_prodring_init()
8507 	tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,  in tg3_rx_prodring_init()
8508 					 TG3_RX_STD_RING_BYTES(tp),  in tg3_rx_prodring_init()
8514 	if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {  in tg3_rx_prodring_init()
8515 		tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),  in tg3_rx_prodring_init()
8520 		tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,  in tg3_rx_prodring_init()
8521 						 TG3_RX_JMB_RING_BYTES(tp),  in tg3_rx_prodring_init()
8531 	tg3_rx_prodring_fini(tp, tpr);  in tg3_rx_prodring_init()
8542 static void tg3_free_rings(struct tg3 *tp)  in tg3_free_rings()  argument
8546 	for (j = 0; j < tp->irq_cnt; j++) {  in tg3_free_rings()
8547 		struct tg3_napi *tnapi = &tp->napi[j];  in tg3_free_rings()
8549 		tg3_rx_prodring_free(tp, &tnapi->prodring);  in tg3_free_rings()
8565 		netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));  in tg3_free_rings()
8576 static int tg3_init_rings(struct tg3 *tp)  in tg3_init_rings()  argument
8581 	tg3_free_rings(tp);  in tg3_init_rings()
8583 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_init_rings()
8584 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_init_rings()
8599 			memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));  in tg3_init_rings()
8602 		    tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {  in tg3_init_rings()
8603 			tg3_free_rings(tp);  in tg3_init_rings()
8611 static void tg3_mem_tx_release(struct tg3 *tp)  in tg3_mem_tx_release()  argument
8615 	for (i = 0; i < tp->irq_max; i++) {  in tg3_mem_tx_release()
8616 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_mem_tx_release()
8619 			dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,  in tg3_mem_tx_release()
8629 static int tg3_mem_tx_acquire(struct tg3 *tp)  in tg3_mem_tx_acquire()  argument
8632 	struct tg3_napi *tnapi = &tp->napi[0];  in tg3_mem_tx_acquire()
8637 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_mem_tx_acquire()
8640 	for (i = 0; i < tp->txq_cnt; i++, tnapi++) {  in tg3_mem_tx_acquire()
8647 		tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,  in tg3_mem_tx_acquire()
8658 	tg3_mem_tx_release(tp);  in tg3_mem_tx_acquire()
8662 static void tg3_mem_rx_release(struct tg3 *tp)  in tg3_mem_rx_release()  argument
8666 	for (i = 0; i < tp->irq_max; i++) {  in tg3_mem_rx_release()
8667 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_mem_rx_release()
8669 		tg3_rx_prodring_fini(tp, &tnapi->prodring);  in tg3_mem_rx_release()
8674 		dma_free_coherent(&tp->pdev->dev,  in tg3_mem_rx_release()
8675 				  TG3_RX_RCB_RING_BYTES(tp),  in tg3_mem_rx_release()
8682 static int tg3_mem_rx_acquire(struct tg3 *tp)  in tg3_mem_rx_acquire()  argument
8686 	limit = tp->rxq_cnt;  in tg3_mem_rx_acquire()
8691 	if (tg3_flag(tp, ENABLE_RSS))  in tg3_mem_rx_acquire()
8695 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_mem_rx_acquire()
8697 		if (tg3_rx_prodring_init(tp, &tnapi->prodring))  in tg3_mem_rx_acquire()
8704 		if (!i && tg3_flag(tp, ENABLE_RSS))  in tg3_mem_rx_acquire()
8707 		tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,  in tg3_mem_rx_acquire()
8708 						    TG3_RX_RCB_RING_BYTES(tp),  in tg3_mem_rx_acquire()
8718 	tg3_mem_rx_release(tp);  in tg3_mem_rx_acquire()
8726 static void tg3_free_consistent(struct tg3 *tp)  in tg3_free_consistent()  argument
8730 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_free_consistent()
8731 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_free_consistent()
8734 			dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,  in tg3_free_consistent()
8741 	tg3_mem_rx_release(tp);  in tg3_free_consistent()
8742 	tg3_mem_tx_release(tp);  in tg3_free_consistent()
8748 	if (tp->hw_stats) {  in tg3_free_consistent()
8749 		dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),  in tg3_free_consistent()
8750 				  tp->hw_stats, tp->stats_mapping);  in tg3_free_consistent()
8751 		tp->hw_stats = NULL;  in tg3_free_consistent()
8759 static int tg3_alloc_consistent(struct tg3 *tp)  in tg3_alloc_consistent()  argument
8763 	tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,  in tg3_alloc_consistent()
8765 					   &tp->stats_mapping, GFP_KERNEL);  in tg3_alloc_consistent()
8766 	if (!tp->hw_stats)  in tg3_alloc_consistent()
8769 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_alloc_consistent()
8770 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_alloc_consistent()
8773 		tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,  in tg3_alloc_consistent()
8782 		if (tg3_flag(tp, ENABLE_RSS)) {  in tg3_alloc_consistent()
8811 	if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))  in tg3_alloc_consistent()
8817 	tg3_free_consistent(tp);  in tg3_alloc_consistent()
8826 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)  in tg3_stop_block()  argument
8831 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_stop_block()
8853 		if (pci_channel_offline(tp->pdev)) {  in tg3_stop_block()
8854 			dev_err(&tp->pdev->dev,  in tg3_stop_block()
8868 		dev_err(&tp->pdev->dev,  in tg3_stop_block()
8878 static int tg3_abort_hw(struct tg3 *tp, bool silent)  in tg3_abort_hw()  argument
8882 	tg3_disable_ints(tp);  in tg3_abort_hw()
8884 	if (pci_channel_offline(tp->pdev)) {  in tg3_abort_hw()
8885 		tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);  in tg3_abort_hw()
8886 		tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;  in tg3_abort_hw()
8891 	tp->rx_mode &= ~RX_MODE_ENABLE;  in tg3_abort_hw()
8892 	tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_abort_hw()
8895 	err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);  in tg3_abort_hw()
8896 	err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);  in tg3_abort_hw()
8897 	err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);  in tg3_abort_hw()
8898 	err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);  in tg3_abort_hw()
8899 	err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);  in tg3_abort_hw()
8900 	err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);  in tg3_abort_hw()
8902 	err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);  in tg3_abort_hw()
8903 	err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);  in tg3_abort_hw()
8904 	err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);  in tg3_abort_hw()
8905 	err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8906 	err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8907 	err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8908 	err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);  in tg3_abort_hw()
8910 	tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;  in tg3_abort_hw()
8911 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_abort_hw()
8914 	tp->tx_mode &= ~TX_MODE_ENABLE;  in tg3_abort_hw()
8915 	tw32_f(MAC_TX_MODE, tp->tx_mode);  in tg3_abort_hw()
8923 		dev_err(&tp->pdev->dev,  in tg3_abort_hw()
8929 	err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);  in tg3_abort_hw()
8930 	err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8931 	err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);  in tg3_abort_hw()
8936 	err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);  in tg3_abort_hw()
8937 	err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);  in tg3_abort_hw()
8940 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_abort_hw()
8941 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_abort_hw()
8950 static void tg3_save_pci_state(struct tg3 *tp)  in tg3_save_pci_state()  argument
8952 	pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);  in tg3_save_pci_state()
8956 static void tg3_restore_pci_state(struct tg3 *tp)  in tg3_restore_pci_state()  argument
8961 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_restore_pci_state()
8962 			       tp->misc_host_ctrl);  in tg3_restore_pci_state()
8966 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&  in tg3_restore_pci_state()
8967 	    tg3_flag(tp, PCIX_MODE))  in tg3_restore_pci_state()
8970 	if (tg3_flag(tp, ENABLE_APE))  in tg3_restore_pci_state()
8974 	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);  in tg3_restore_pci_state()
8976 	pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);  in tg3_restore_pci_state()
8978 	if (!tg3_flag(tp, PCI_EXPRESS)) {  in tg3_restore_pci_state()
8979 		pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,  in tg3_restore_pci_state()
8980 				      tp->pci_cacheline_sz);  in tg3_restore_pci_state()
8981 		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,  in tg3_restore_pci_state()
8982 				      tp->pci_lat_timer);  in tg3_restore_pci_state()
8986 	if (tg3_flag(tp, PCIX_MODE)) {  in tg3_restore_pci_state()
8989 		pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_restore_pci_state()
8992 		pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_restore_pci_state()
8996 	if (tg3_flag(tp, 5780_CLASS)) {  in tg3_restore_pci_state()
9001 		if (tg3_flag(tp, USING_MSI)) {  in tg3_restore_pci_state()
9004 			pci_read_config_word(tp->pdev,  in tg3_restore_pci_state()
9005 					     tp->msi_cap + PCI_MSI_FLAGS,  in tg3_restore_pci_state()
9007 			pci_write_config_word(tp->pdev,  in tg3_restore_pci_state()
9008 					      tp->msi_cap + PCI_MSI_FLAGS,  in tg3_restore_pci_state()
9016 static void tg3_override_clk(struct tg3 *tp)  in tg3_override_clk()  argument
9020 	switch (tg3_asic_rev(tp)) {  in tg3_override_clk()
9037 static void tg3_restore_clk(struct tg3 *tp)  in tg3_restore_clk()  argument
9041 	switch (tg3_asic_rev(tp)) {  in tg3_restore_clk()
9060 static int tg3_chip_reset(struct tg3 *tp)  in tg3_chip_reset()  argument
9061 	__releases(tp->lock)  in tg3_chip_reset()
9062 	__acquires(tp->lock)  in tg3_chip_reset()
9068 	if (!pci_device_is_present(tp->pdev))  in tg3_chip_reset()
9071 	tg3_nvram_lock(tp);  in tg3_chip_reset()
9073 	tg3_ape_lock(tp, TG3_APE_LOCK_GRC);  in tg3_chip_reset()
9078 	tp->nvram_lock_cnt = 0;  in tg3_chip_reset()
9084 	tg3_save_pci_state(tp);  in tg3_chip_reset()
9086 	if (tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_chip_reset()
9087 	    tg3_flag(tp, 5755_PLUS))  in tg3_chip_reset()
9096 	write_op = tp->write32;  in tg3_chip_reset()
9098 		tp->write32 = tg3_write32;  in tg3_chip_reset()
9106 	tg3_flag_set(tp, CHIP_RESETTING);  in tg3_chip_reset()
9107 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_chip_reset()
9108 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_chip_reset()
9118 	tg3_full_unlock(tp);  in tg3_chip_reset()
9120 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_chip_reset()
9121 		synchronize_irq(tp->napi[i].irq_vec);  in tg3_chip_reset()
9123 	tg3_full_lock(tp, 0);  in tg3_chip_reset()
9125 	if (tg3_asic_rev(tp) == ASIC_REV_57780) {  in tg3_chip_reset()
9133 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_chip_reset()
9135 		if (tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_chip_reset()
9136 		    !tg3_flag(tp, 57765_PLUS) &&  in tg3_chip_reset()
9141 		if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {  in tg3_chip_reset()
9147 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_chip_reset()
9158 	tg3_override_clk(tp);  in tg3_chip_reset()
9161 	if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))  in tg3_chip_reset()
9167 	tp->write32 = write_op;  in tg3_chip_reset()
9190 	pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);  in tg3_chip_reset()
9194 	if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {  in tg3_chip_reset()
9197 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {  in tg3_chip_reset()
9205 			pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);  in tg3_chip_reset()
9206 			pci_write_config_dword(tp->pdev, 0xc4,  in tg3_chip_reset()
9216 		if (!tg3_flag(tp, CPMU_PRESENT))  in tg3_chip_reset()
9218 		pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);  in tg3_chip_reset()
9221 		pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,  in tg3_chip_reset()
9228 	tg3_restore_pci_state(tp);  in tg3_chip_reset()
9230 	tg3_flag_clear(tp, CHIP_RESETTING);  in tg3_chip_reset()
9231 	tg3_flag_clear(tp, ERROR_PROCESSED);  in tg3_chip_reset()
9234 	if (tg3_flag(tp, 5780_CLASS))  in tg3_chip_reset()
9238 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {  in tg3_chip_reset()
9239 		tg3_stop_fw(tp);  in tg3_chip_reset()
9243 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_chip_reset()
9249 		tg3_stop_fw(tp);  in tg3_chip_reset()
9250 		tg3_halt_cpu(tp, RX_CPU_BASE);  in tg3_chip_reset()
9253 	err = tg3_poll_fw(tp);  in tg3_chip_reset()
9257 	tw32(GRC_MODE, tp->grc_mode);  in tg3_chip_reset()
9259 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {  in tg3_chip_reset()
9265 	if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&  in tg3_chip_reset()
9266 	    tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_chip_reset()
9267 		tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;  in tg3_chip_reset()
9268 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)  in tg3_chip_reset()
9269 			tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;  in tg3_chip_reset()
9270 		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);  in tg3_chip_reset()
9273 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_chip_reset()
9274 		tp->mac_mode = MAC_MODE_PORT_MODE_TBI;  in tg3_chip_reset()
9275 		val = tp->mac_mode;  in tg3_chip_reset()
9276 	} else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {  in tg3_chip_reset()
9277 		tp->mac_mode = MAC_MODE_PORT_MODE_GMII;  in tg3_chip_reset()
9278 		val = tp->mac_mode;  in tg3_chip_reset()
9285 	tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);  in tg3_chip_reset()
9287 	tg3_mdio_start(tp);  in tg3_chip_reset()
9289 	if (tg3_flag(tp, PCI_EXPRESS) &&  in tg3_chip_reset()
9290 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&  in tg3_chip_reset()
9291 	    tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_chip_reset()
9292 	    !tg3_flag(tp, 57765_PLUS)) {  in tg3_chip_reset()
9298 	tg3_restore_clk(tp);  in tg3_chip_reset()
9303 	if (tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_chip_reset()
9310 	tg3_flag_clear(tp, ENABLE_ASF);  in tg3_chip_reset()
9311 	tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |  in tg3_chip_reset()
9314 	tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);  in tg3_chip_reset()
9315 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);  in tg3_chip_reset()
9319 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);  in tg3_chip_reset()
9321 			tg3_flag_set(tp, ENABLE_ASF);  in tg3_chip_reset()
9322 			tp->last_event_jiffies = jiffies;  in tg3_chip_reset()
9323 			if (tg3_flag(tp, 5750_PLUS))  in tg3_chip_reset()
9324 				tg3_flag_set(tp, ASF_NEW_HANDSHAKE);  in tg3_chip_reset()
9326 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);  in tg3_chip_reset()
9328 				tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;  in tg3_chip_reset()
9330 				tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;  in tg3_chip_reset()
9342 static int tg3_halt(struct tg3 *tp, int kind, bool silent)  in tg3_halt()  argument
9346 	tg3_stop_fw(tp);  in tg3_halt()
9348 	tg3_write_sig_pre_reset(tp, kind);  in tg3_halt()
9350 	tg3_abort_hw(tp, silent);  in tg3_halt()
9351 	err = tg3_chip_reset(tp);  in tg3_halt()
9353 	__tg3_set_mac_addr(tp, false);  in tg3_halt()
9355 	tg3_write_sig_legacy(tp, kind);  in tg3_halt()
9356 	tg3_write_sig_post_reset(tp, kind);  in tg3_halt()
9358 	if (tp->hw_stats) {  in tg3_halt()
9360 		tg3_get_nstats(tp, &tp->net_stats_prev);  in tg3_halt()
9361 		tg3_get_estats(tp, &tp->estats_prev);  in tg3_halt()
9364 		memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));  in tg3_halt()
9372 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_mac_addr()  local
9385 	if (tg3_flag(tp, ENABLE_ASF)) {  in tg3_set_mac_addr()
9398 	spin_lock_bh(&tp->lock);  in tg3_set_mac_addr()
9399 	__tg3_set_mac_addr(tp, skip_mac_1);  in tg3_set_mac_addr()
9401 	spin_unlock_bh(&tp->lock);  in tg3_set_mac_addr()
9407 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,  in tg3_set_bdinfo()  argument
9411 	tg3_write_mem(tp,  in tg3_set_bdinfo()
9414 	tg3_write_mem(tp,  in tg3_set_bdinfo()
9417 	tg3_write_mem(tp,  in tg3_set_bdinfo()
9421 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_set_bdinfo()
9422 		tg3_write_mem(tp,  in tg3_set_bdinfo()
9428 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)  in tg3_coal_tx_init()  argument
9432 	if (!tg3_flag(tp, ENABLE_TSS)) {  in tg3_coal_tx_init()
9441 		for (; i < tp->txq_cnt; i++) {  in tg3_coal_tx_init()
9453 	for (; i < tp->irq_max - 1; i++) {  in tg3_coal_tx_init()
9460 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)  in tg3_coal_rx_init()  argument
9463 	u32 limit = tp->rxq_cnt;  in tg3_coal_rx_init()
9465 	if (!tg3_flag(tp, ENABLE_RSS)) {  in tg3_coal_rx_init()
9487 	for (; i < tp->irq_max - 1; i++) {  in tg3_coal_rx_init()
9494 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)  in __tg3_set_coalesce()  argument
9496 	tg3_coal_tx_init(tp, ec);  in __tg3_set_coalesce()
9497 	tg3_coal_rx_init(tp, ec);  in __tg3_set_coalesce()
9499 	if (!tg3_flag(tp, 5705_PLUS)) {  in __tg3_set_coalesce()
9505 		if (!tp->link_up)  in __tg3_set_coalesce()
9513 static void tg3_tx_rcbs_disable(struct tg3 *tp)  in tg3_tx_rcbs_disable()  argument
9518 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_tx_rcbs_disable()
9520 	else if (tg3_flag(tp, 5717_PLUS))  in tg3_tx_rcbs_disable()
9522 	else if (tg3_flag(tp, 57765_CLASS) ||  in tg3_tx_rcbs_disable()
9523 		 tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_tx_rcbs_disable()
9530 		tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,  in tg3_tx_rcbs_disable()
9535 static void tg3_tx_rcbs_init(struct tg3 *tp)  in tg3_tx_rcbs_init()  argument
9540 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_tx_rcbs_init()
9543 	for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {  in tg3_tx_rcbs_init()
9544 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_tx_rcbs_init()
9549 		tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,  in tg3_tx_rcbs_init()
9556 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)  in tg3_rx_ret_rcbs_disable()  argument
9561 	if (tg3_flag(tp, 5717_PLUS))  in tg3_rx_ret_rcbs_disable()
9563 	else if (!tg3_flag(tp, 5705_PLUS))  in tg3_rx_ret_rcbs_disable()
9565 	else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_rx_ret_rcbs_disable()
9566 		 tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_rx_ret_rcbs_disable()
9567 		 tg3_flag(tp, 57765_CLASS))  in tg3_rx_ret_rcbs_disable()
9574 		tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,  in tg3_rx_ret_rcbs_disable()
9579 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)  in tg3_rx_ret_rcbs_init()  argument
9584 	if (tg3_flag(tp, ENABLE_RSS))  in tg3_rx_ret_rcbs_init()
9587 	for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {  in tg3_rx_ret_rcbs_init()
9588 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_rx_ret_rcbs_init()
9593 		tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,  in tg3_rx_ret_rcbs_init()
9594 			       (tp->rx_ret_ring_mask + 1) <<  in tg3_rx_ret_rcbs_init()
9600 static void tg3_rings_reset(struct tg3 *tp)  in tg3_rings_reset()  argument
9604 	struct tg3_napi *tnapi = &tp->napi[0];  in tg3_rings_reset()
9606 	tg3_tx_rcbs_disable(tp);  in tg3_rings_reset()
9608 	tg3_rx_ret_rcbs_disable(tp);  in tg3_rings_reset()
9611 	tw32_mailbox_f(tp->napi[0].int_mbox, 1);  in tg3_rings_reset()
9612 	tp->napi[0].chk_msi_cnt = 0;  in tg3_rings_reset()
9613 	tp->napi[0].last_rx_cons = 0;  in tg3_rings_reset()
9614 	tp->napi[0].last_tx_cons = 0;  in tg3_rings_reset()
9617 	if (tg3_flag(tp, SUPPORT_MSIX)) {  in tg3_rings_reset()
9618 		for (i = 1; i < tp->irq_max; i++) {  in tg3_rings_reset()
9619 			tp->napi[i].tx_prod = 0;  in tg3_rings_reset()
9620 			tp->napi[i].tx_cons = 0;  in tg3_rings_reset()
9621 			if (tg3_flag(tp, ENABLE_TSS))  in tg3_rings_reset()
9622 				tw32_mailbox(tp->napi[i].prodmbox, 0);  in tg3_rings_reset()
9623 			tw32_rx_mbox(tp->napi[i].consmbox, 0);  in tg3_rings_reset()
9624 			tw32_mailbox_f(tp->napi[i].int_mbox, 1);  in tg3_rings_reset()
9625 			tp->napi[i].chk_msi_cnt = 0;  in tg3_rings_reset()
9626 			tp->napi[i].last_rx_cons = 0;  in tg3_rings_reset()
9627 			tp->napi[i].last_tx_cons = 0;  in tg3_rings_reset()
9629 		if (!tg3_flag(tp, ENABLE_TSS))  in tg3_rings_reset()
9630 			tw32_mailbox(tp->napi[0].prodmbox, 0);  in tg3_rings_reset()
9632 		tp->napi[0].tx_prod = 0;  in tg3_rings_reset()
9633 		tp->napi[0].tx_cons = 0;  in tg3_rings_reset()
9634 		tw32_mailbox(tp->napi[0].prodmbox, 0);  in tg3_rings_reset()
9635 		tw32_rx_mbox(tp->napi[0].consmbox, 0);  in tg3_rings_reset()
9639 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_rings_reset()
9656 	for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {  in tg3_rings_reset()
9666 	tg3_tx_rcbs_init(tp);  in tg3_rings_reset()
9667 	tg3_rx_ret_rcbs_init(tp);  in tg3_rings_reset()
9670 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)  in tg3_setup_rxbd_thresholds()  argument
9674 	if (!tg3_flag(tp, 5750_PLUS) ||  in tg3_setup_rxbd_thresholds()
9675 	    tg3_flag(tp, 5780_CLASS) ||  in tg3_setup_rxbd_thresholds()
9676 	    tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_setup_rxbd_thresholds()
9677 	    tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_setup_rxbd_thresholds()
9678 	    tg3_flag(tp, 57765_PLUS))  in tg3_setup_rxbd_thresholds()
9680 	else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_setup_rxbd_thresholds()
9681 		 tg3_asic_rev(tp) == ASIC_REV_5787)  in tg3_setup_rxbd_thresholds()
9686 	nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);  in tg3_setup_rxbd_thresholds()
9687 	host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);  in tg3_setup_rxbd_thresholds()
9692 	if (tg3_flag(tp, 57765_PLUS))  in tg3_setup_rxbd_thresholds()
9695 	if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))  in tg3_setup_rxbd_thresholds()
9700 	host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);  in tg3_setup_rxbd_thresholds()
9705 	if (tg3_flag(tp, 57765_PLUS))  in tg3_setup_rxbd_thresholds()
9733 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)  in tg3_set_multi()  argument
9744 	struct tg3 *tp = netdev_priv(dev);  in __tg3_set_rx_mode()  local
9747 	rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |  in __tg3_set_rx_mode()
9754 	if (!tg3_flag(tp, ENABLE_ASF))  in __tg3_set_rx_mode()
9763 		tg3_set_multi(tp, 1);  in __tg3_set_rx_mode()
9766 		tg3_set_multi(tp, 0);  in __tg3_set_rx_mode()
9789 	if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {  in __tg3_set_rx_mode()
9797 			__tg3_set_one_mac_addr(tp, ha->addr,  in __tg3_set_rx_mode()
9798 					       i + TG3_UCAST_ADDR_IDX(tp));  in __tg3_set_rx_mode()
9803 	if (rx_mode != tp->rx_mode) {  in __tg3_set_rx_mode()
9804 		tp->rx_mode = rx_mode;  in __tg3_set_rx_mode()
9810 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)  in tg3_rss_init_dflt_indir_tbl()  argument
9815 		tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);  in tg3_rss_init_dflt_indir_tbl()
9818 static void tg3_rss_check_indir_tbl(struct tg3 *tp)  in tg3_rss_check_indir_tbl()  argument
9822 	if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_rss_check_indir_tbl()
9825 	if (tp->rxq_cnt == 1) {  in tg3_rss_check_indir_tbl()
9826 		memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));  in tg3_rss_check_indir_tbl()
9832 		if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)  in tg3_rss_check_indir_tbl()
9837 		tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);  in tg3_rss_check_indir_tbl()
9840 static void tg3_rss_write_indir_tbl(struct tg3 *tp)  in tg3_rss_write_indir_tbl()  argument
9846 		u32 val = tp->rss_ind_tbl[i];  in tg3_rss_write_indir_tbl()
9850 			val |= tp->rss_ind_tbl[i];  in tg3_rss_write_indir_tbl()
9857 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)  in tg3_lso_rd_dma_workaround_bit()  argument
9859 	if (tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_lso_rd_dma_workaround_bit()
9866 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)  in tg3_reset_hw()  argument
9870 	struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;  in tg3_reset_hw()
9872 	tg3_disable_ints(tp);  in tg3_reset_hw()
9874 	tg3_stop_fw(tp);  in tg3_reset_hw()
9876 	tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);  in tg3_reset_hw()
9878 	if (tg3_flag(tp, INIT_COMPLETE))  in tg3_reset_hw()
9879 		tg3_abort_hw(tp, 1);  in tg3_reset_hw()
9881 	if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&  in tg3_reset_hw()
9882 	    !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {  in tg3_reset_hw()
9883 		tg3_phy_pull_config(tp);  in tg3_reset_hw()
9884 		tg3_eee_pull_config(tp, NULL);  in tg3_reset_hw()
9885 		tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_reset_hw()
9889 	if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)  in tg3_reset_hw()
9890 		tg3_setup_eee(tp);  in tg3_reset_hw()
9893 		tg3_phy_reset(tp);  in tg3_reset_hw()
9895 	err = tg3_chip_reset(tp);  in tg3_reset_hw()
9899 	tg3_write_sig_legacy(tp, RESET_KIND_INIT);  in tg3_reset_hw()
9901 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {  in tg3_reset_hw()
9922 	if (tg3_asic_rev(tp) == ASIC_REV_57780) {  in tg3_reset_hw()
9937 	if (tg3_flag(tp, L1PLLPD_EN)) {  in tg3_reset_hw()
9951 	if (tg3_flag(tp, 57765_CLASS)) {  in tg3_reset_hw()
9952 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {  in tg3_reset_hw()
9967 		if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {  in tg3_reset_hw()
10001 	if (!tg3_flag(tp, CPMU_PRESENT)) {  in tg3_reset_hw()
10002 		if (!tg3_flag(tp, PCI_EXPRESS))  in tg3_reset_hw()
10003 			tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;  in tg3_reset_hw()
10004 		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);  in tg3_reset_hw()
10007 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&  in tg3_reset_hw()
10008 	    tg3_flag(tp, PCIX_MODE)) {  in tg3_reset_hw()
10014 	if (tg3_flag(tp, ENABLE_APE)) {  in tg3_reset_hw()
10025 	if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {  in tg3_reset_hw()
10037 	err = tg3_init_rings(tp);  in tg3_reset_hw()
10041 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_reset_hw()
10044 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)  in tg3_reset_hw()
10046 		if (!tg3_flag(tp, 57765_CLASS) &&  in tg3_reset_hw()
10047 		    tg3_asic_rev(tp) != ASIC_REV_5717 &&  in tg3_reset_hw()
10048 		    tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_reset_hw()
10050 		tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);  in tg3_reset_hw()
10051 	} else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&  in tg3_reset_hw()
10052 		   tg3_asic_rev(tp) != ASIC_REV_5761) {  in tg3_reset_hw()
10056 		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_reset_hw()
10059 	tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |  in tg3_reset_hw()
10063 	tp->grc_mode |= GRC_MODE_HOST_SENDBDS;  in tg3_reset_hw()
10071 	tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;  in tg3_reset_hw()
10074 	if (tp->rxptpctl)  in tg3_reset_hw()
10076 		     tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);  in tg3_reset_hw()
10078 	if (tg3_flag(tp, PTP_CAPABLE))  in tg3_reset_hw()
10081 	tw32(GRC_MODE, tp->grc_mode | val);  in tg3_reset_hw()
10087 	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&  in tg3_reset_hw()
10088 	    tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {  in tg3_reset_hw()
10100 	if (tg3_flag(tp, 5750_PLUS)) {  in tg3_reset_hw()
10102 	} else if (tg3_asic_rev(tp) != ASIC_REV_5705) {  in tg3_reset_hw()
10104 		if (tg3_asic_rev(tp) == ASIC_REV_5704)  in tg3_reset_hw()
10110 	} else if (tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10113 		fw_len = tp->fw_len;  in tg3_reset_hw()
10121 	if (tp->dev->mtu <= ETH_DATA_LEN) {  in tg3_reset_hw()
10123 		     tp->bufmgr_config.mbuf_read_dma_low_water);  in tg3_reset_hw()
10125 		     tp->bufmgr_config.mbuf_mac_rx_low_water);  in tg3_reset_hw()
10127 		     tp->bufmgr_config.mbuf_high_water);  in tg3_reset_hw()
10130 		     tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);  in tg3_reset_hw()
10132 		     tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);  in tg3_reset_hw()
10134 		     tp->bufmgr_config.mbuf_high_water_jumbo);  in tg3_reset_hw()
10137 	     tp->bufmgr_config.dma_low_water);  in tg3_reset_hw()
10139 	     tp->bufmgr_config.dma_high_water);  in tg3_reset_hw()
10142 	if (tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_reset_hw()
10144 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_reset_hw()
10145 	    tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_reset_hw()
10146 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_reset_hw()
10147 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)  in tg3_reset_hw()
10156 		netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);  in tg3_reset_hw()
10160 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)  in tg3_reset_hw()
10163 	tg3_setup_rxbd_thresholds(tp);  in tg3_reset_hw()
10186 	if (!tg3_flag(tp, 5717_PLUS))  in tg3_reset_hw()
10191 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_reset_hw()
10198 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_reset_hw()
10199 	    (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {  in tg3_reset_hw()
10201 		if (tg3_flag(tp, JUMBO_RING_ENABLE)) {  in tg3_reset_hw()
10206 			val = TG3_RX_JMB_RING_SIZE(tp) <<  in tg3_reset_hw()
10210 			if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||  in tg3_reset_hw()
10211 			    tg3_flag(tp, 57765_CLASS) ||  in tg3_reset_hw()
10212 			    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10220 		if (tg3_flag(tp, 57765_PLUS)) {  in tg3_reset_hw()
10221 			val = TG3_RX_STD_RING_SIZE(tp);  in tg3_reset_hw()
10231 	tpr->rx_std_prod_idx = tp->rx_pending;  in tg3_reset_hw()
10235 		tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;  in tg3_reset_hw()
10238 	tg3_rings_reset(tp);  in tg3_reset_hw()
10241 	__tg3_set_mac_addr(tp, false);  in tg3_reset_hw()
10245 	     tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);  in tg3_reset_hw()
10254 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10255 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10275 	if (tg3_asic_rev(tp) == ASIC_REV_5717)  in tg3_reset_hw()
10278 	if (tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_reset_hw()
10279 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_reset_hw()
10280 	    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_reset_hw()
10285 	if (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_reset_hw()
10286 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {  in tg3_reset_hw()
10287 		if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_reset_hw()
10288 		    tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_reset_hw()
10291 			   !tg3_flag(tp, IS_5788)) {  in tg3_reset_hw()
10296 	if (tg3_flag(tp, PCI_EXPRESS))  in tg3_reset_hw()
10299 	if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_reset_hw()
10300 		tp->dma_limit = 0;  in tg3_reset_hw()
10301 		if (tp->dev->mtu <= ETH_DATA_LEN) {  in tg3_reset_hw()
10303 			tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;  in tg3_reset_hw()
10307 	if (tg3_flag(tp, HW_TSO_1) ||  in tg3_reset_hw()
10308 	    tg3_flag(tp, HW_TSO_2) ||  in tg3_reset_hw()
10309 	    tg3_flag(tp, HW_TSO_3))  in tg3_reset_hw()
10312 	if (tg3_flag(tp, 57765_PLUS) ||  in tg3_reset_hw()
10313 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_reset_hw()
10314 	    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_reset_hw()
10317 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10318 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10321 	if (tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_reset_hw()
10322 	    tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_reset_hw()
10323 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_reset_hw()
10324 	    tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_reset_hw()
10325 	    tg3_flag(tp, 57765_PLUS)) {  in tg3_reset_hw()
10328 		if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10334 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_reset_hw()
10335 		    tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_reset_hw()
10346 	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_reset_hw()
10347 	    tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10348 	    tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_reset_hw()
10351 		if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10363 	if (tg3_flag(tp, 5750_PLUS)) {  in tg3_reset_hw()
10368 		   tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10389 	__tg3_set_coalesce(tp, &tp->coal);  in tg3_reset_hw()
10391 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_reset_hw()
10397 		     ((u64) tp->stats_mapping >> 32));  in tg3_reset_hw()
10399 		     ((u64) tp->stats_mapping & 0xffffffff));  in tg3_reset_hw()
10408 			tg3_write_mem(tp, i, 0);  in tg3_reset_hw()
10413 	tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);  in tg3_reset_hw()
10417 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_reset_hw()
10420 	if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {  in tg3_reset_hw()
10421 		tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_reset_hw()
10427 	tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |  in tg3_reset_hw()
10430 	if (tg3_flag(tp, ENABLE_APE))  in tg3_reset_hw()
10431 		tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;  in tg3_reset_hw()
10432 	if (!tg3_flag(tp, 5705_PLUS) &&  in tg3_reset_hw()
10433 	    !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_reset_hw()
10434 	    tg3_asic_rev(tp) != ASIC_REV_5700)  in tg3_reset_hw()
10435 		tp->mac_mode |= MAC_MODE_LINK_POLARITY;  in tg3_reset_hw()
10436 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);  in tg3_reset_hw()
10445 	if (!tg3_flag(tp, IS_NIC)) {  in tg3_reset_hw()
10452 		if (tg3_asic_rev(tp) == ASIC_REV_5752)  in tg3_reset_hw()
10456 		if (tg3_asic_rev(tp) == ASIC_REV_5755)  in tg3_reset_hw()
10459 		tp->grc_local_ctrl &= ~gpio_mask;  in tg3_reset_hw()
10460 		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;  in tg3_reset_hw()
10463 		if (tg3_flag(tp, EEPROM_WRITE_PROT))  in tg3_reset_hw()
10464 			tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |  in tg3_reset_hw()
10467 	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);  in tg3_reset_hw()
10470 	if (tg3_flag(tp, USING_MSIX)) {  in tg3_reset_hw()
10473 		if (tp->irq_cnt > 1)  in tg3_reset_hw()
10475 		if (!tg3_flag(tp, 1SHOT_MSI))  in tg3_reset_hw()
10480 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_reset_hw()
10491 	if (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_reset_hw()
10492 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {  in tg3_reset_hw()
10493 		if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_reset_hw()
10494 		    (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||  in tg3_reset_hw()
10495 		     tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {  in tg3_reset_hw()
10498 			   !tg3_flag(tp, IS_5788)) {  in tg3_reset_hw()
10504 	if (tg3_flag(tp, 5755_PLUS))  in tg3_reset_hw()
10507 	if (tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_reset_hw()
10513 	if (tg3_flag(tp, PCIX_MODE)) {  in tg3_reset_hw()
10516 		pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_reset_hw()
10518 		if (tg3_asic_rev(tp) == ASIC_REV_5703) {  in tg3_reset_hw()
10521 		} else if (tg3_asic_rev(tp) == ASIC_REV_5704) {  in tg3_reset_hw()
10525 		pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_reset_hw()
10532 	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_reset_hw()
10533 	    tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_reset_hw()
10535 			if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))  in tg3_reset_hw()
10540 			val |= tg3_lso_rd_dma_workaround_bit(tp);  in tg3_reset_hw()
10542 			tg3_flag_set(tp, 5719_5720_RDMA_BUG);  in tg3_reset_hw()
10547 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_reset_hw()
10550 	if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_reset_hw()
10559 	if (tg3_flag(tp, LRG_PROD_RING_CAP))  in tg3_reset_hw()
10563 	if (tg3_flag(tp, HW_TSO_1) ||  in tg3_reset_hw()
10564 	    tg3_flag(tp, HW_TSO_2) ||  in tg3_reset_hw()
10565 	    tg3_flag(tp, HW_TSO_3))  in tg3_reset_hw()
10568 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_reset_hw()
10573 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {  in tg3_reset_hw()
10574 		err = tg3_load_5701_a0_firmware_fix(tp);  in tg3_reset_hw()
10579 	if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_reset_hw()
10583 		tg3_load_57766_firmware(tp);  in tg3_reset_hw()
10586 	if (tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10587 		err = tg3_load_tso_firmware(tp);  in tg3_reset_hw()
10592 	tp->tx_mode = TX_MODE_ENABLE;  in tg3_reset_hw()
10594 	if (tg3_flag(tp, 5755_PLUS) ||  in tg3_reset_hw()
10595 	    tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_reset_hw()
10596 		tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;  in tg3_reset_hw()
10598 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10599 	    tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_reset_hw()
10601 		tp->tx_mode &= ~val;  in tg3_reset_hw()
10602 		tp->tx_mode |= tr32(MAC_TX_MODE) & val;  in tg3_reset_hw()
10605 	tw32_f(MAC_TX_MODE, tp->tx_mode);  in tg3_reset_hw()
10608 	if (tg3_flag(tp, ENABLE_RSS)) {  in tg3_reset_hw()
10611 		tg3_rss_write_indir_tbl(tp);  in tg3_reset_hw()
10619 	tp->rx_mode = RX_MODE_ENABLE;  in tg3_reset_hw()
10620 	if (tg3_flag(tp, 5755_PLUS))  in tg3_reset_hw()
10621 		tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;  in tg3_reset_hw()
10623 	if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10624 		tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;  in tg3_reset_hw()
10626 	if (tg3_flag(tp, ENABLE_RSS))  in tg3_reset_hw()
10627 		tp->rx_mode |= RX_MODE_RSS_ENABLE |  in tg3_reset_hw()
10634 	tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_reset_hw()
10637 	tw32(MAC_LED_CTRL, tp->led_ctrl);  in tg3_reset_hw()
10640 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_reset_hw()
10644 	tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_reset_hw()
10647 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_reset_hw()
10648 		if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&  in tg3_reset_hw()
10649 		    !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {  in tg3_reset_hw()
10657 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)  in tg3_reset_hw()
10664 	if (tg3_flag(tp, 57765_CLASS))  in tg3_reset_hw()
10670 	if (tg3_asic_rev(tp) == ASIC_REV_5704 &&  in tg3_reset_hw()
10671 	    (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {  in tg3_reset_hw()
10673 		tg3_flag_set(tp, HW_AUTONEG);  in tg3_reset_hw()
10676 	if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_reset_hw()
10677 	    tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_reset_hw()
10682 		tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;  in tg3_reset_hw()
10683 		tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;  in tg3_reset_hw()
10684 		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);  in tg3_reset_hw()
10687 	if (!tg3_flag(tp, USE_PHYLIB)) {  in tg3_reset_hw()
10688 		if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)  in tg3_reset_hw()
10689 			tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;  in tg3_reset_hw()
10691 		err = tg3_setup_phy(tp, false);  in tg3_reset_hw()
10695 		if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_reset_hw()
10696 		    !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {  in tg3_reset_hw()
10700 			if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {  in tg3_reset_hw()
10701 				tg3_writephy(tp, MII_TG3_TEST1,  in tg3_reset_hw()
10703 				tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);  in tg3_reset_hw()
10708 	__tg3_set_rx_mode(tp->dev);  in tg3_reset_hw()
10716 	if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))  in tg3_reset_hw()
10720 	if (tg3_flag(tp, ENABLE_ASF))  in tg3_reset_hw()
10770 	if (tg3_flag(tp, ENABLE_APE))  in tg3_reset_hw()
10772 		tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,  in tg3_reset_hw()
10775 	tg3_write_sig_post_reset(tp, RESET_KIND_INIT);  in tg3_reset_hw()
10783 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)  in tg3_init_hw()  argument
10789 	tg3_enable_register_access(tp);  in tg3_init_hw()
10790 	tg3_poll_fw(tp);  in tg3_init_hw()
10792 	tg3_switch_clocks(tp);  in tg3_init_hw()
10796 	return tg3_reset_hw(tp, reset_phy);  in tg3_init_hw()
10800 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)  in tg3_sd_scan_scratchpad()  argument
10807 		tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);  in tg3_sd_scan_scratchpad()
10821 	struct tg3 *tp = dev_get_drvdata(dev);  in tg3_show_temp()  local
10824 	spin_lock_bh(&tp->lock);  in tg3_show_temp()
10825 	tg3_ape_scratchpad_read(tp, &temperature, attr->index,  in tg3_show_temp()
10827 	spin_unlock_bh(&tp->lock);  in tg3_show_temp()
10847 static void tg3_hwmon_close(struct tg3 *tp)  in tg3_hwmon_close()  argument
10849 	if (tp->hwmon_dev) {  in tg3_hwmon_close()
10850 		hwmon_device_unregister(tp->hwmon_dev);  in tg3_hwmon_close()
10851 		tp->hwmon_dev = NULL;  in tg3_hwmon_close()
10855 static void tg3_hwmon_open(struct tg3 *tp)  in tg3_hwmon_open()  argument
10859 	struct pci_dev *pdev = tp->pdev;  in tg3_hwmon_open()
10862 	tg3_sd_scan_scratchpad(tp, ocirs);  in tg3_hwmon_open()
10875 	tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",  in tg3_hwmon_open()
10876 							  tp, tg3_groups);  in tg3_hwmon_open()
10877 	if (IS_ERR(tp->hwmon_dev)) {  in tg3_hwmon_open()
10878 		tp->hwmon_dev = NULL;  in tg3_hwmon_open()
10883 static inline void tg3_hwmon_close(struct tg3 *tp) { }  in tg3_hwmon_close()  argument
10884 static inline void tg3_hwmon_open(struct tg3 *tp) { }  in tg3_hwmon_open()  argument
10895 static void tg3_periodic_fetch_stats(struct tg3 *tp)  in tg3_periodic_fetch_stats()  argument
10897 	struct tg3_hw_stats *sp = tp->hw_stats;  in tg3_periodic_fetch_stats()
10899 	if (!tp->link_up)  in tg3_periodic_fetch_stats()
10915 	if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&  in tg3_periodic_fetch_stats()
10921 		val &= ~tg3_lso_rd_dma_workaround_bit(tp);  in tg3_periodic_fetch_stats()
10923 		tg3_flag_clear(tp, 5719_5720_RDMA_BUG);  in tg3_periodic_fetch_stats()
10942 	if (tg3_asic_rev(tp) != ASIC_REV_5717 &&  in tg3_periodic_fetch_stats()
10943 	    tg3_asic_rev(tp) != ASIC_REV_5762 &&  in tg3_periodic_fetch_stats()
10944 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&  in tg3_periodic_fetch_stats()
10945 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {  in tg3_periodic_fetch_stats()
10961 static void tg3_chk_missed_msi(struct tg3 *tp)  in tg3_chk_missed_msi()  argument
10965 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_chk_missed_msi()
10966 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_chk_missed_msi()
10986 	struct tg3 *tp = from_timer(tp, t, timer);  in tg3_timer()  local
10988 	spin_lock(&tp->lock);  in tg3_timer()
10990 	if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {  in tg3_timer()
10991 		spin_unlock(&tp->lock);  in tg3_timer()
10995 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_timer()
10996 	    tg3_flag(tp, 57765_CLASS))  in tg3_timer()
10997 		tg3_chk_missed_msi(tp);  in tg3_timer()
10999 	if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {  in tg3_timer()
11004 	if (!tg3_flag(tp, TAGGED_STATUS)) {  in tg3_timer()
11009 		if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {  in tg3_timer()
11011 			     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);  in tg3_timer()
11013 			tw32(HOSTCC_MODE, tp->coalesce_mode |  in tg3_timer()
11018 			spin_unlock(&tp->lock);  in tg3_timer()
11019 			tg3_reset_task_schedule(tp);  in tg3_timer()
11025 	if (!--tp->timer_counter) {  in tg3_timer()
11026 		if (tg3_flag(tp, 5705_PLUS))  in tg3_timer()
11027 			tg3_periodic_fetch_stats(tp);  in tg3_timer()
11029 		if (tp->setlpicnt && !--tp->setlpicnt)  in tg3_timer()
11030 			tg3_phy_eee_enable(tp);  in tg3_timer()
11032 		if (tg3_flag(tp, USE_LINKCHG_REG)) {  in tg3_timer()
11039 			if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {  in tg3_timer()
11046 				tg3_setup_phy(tp, false);  in tg3_timer()
11047 		} else if (tg3_flag(tp, POLL_SERDES)) {  in tg3_timer()
11051 			if (tp->link_up &&  in tg3_timer()
11055 			if (!tp->link_up &&  in tg3_timer()
11061 				if (!tp->serdes_counter) {  in tg3_timer()
11063 					     (tp->mac_mode &  in tg3_timer()
11066 					tw32_f(MAC_MODE, tp->mac_mode);  in tg3_timer()
11069 				tg3_setup_phy(tp, false);  in tg3_timer()
11071 		} else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_timer()
11072 			   tg3_flag(tp, 5780_CLASS)) {  in tg3_timer()
11073 			tg3_serdes_parallel_detect(tp);  in tg3_timer()
11074 		} else if (tg3_flag(tp, POLL_CPMU_LINK)) {  in tg3_timer()
11079 			if (link_up != tp->link_up)  in tg3_timer()
11080 				tg3_setup_phy(tp, false);  in tg3_timer()
11083 		tp->timer_counter = tp->timer_multiplier;  in tg3_timer()
11103 	if (!--tp->asf_counter) {  in tg3_timer()
11104 		if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {  in tg3_timer()
11105 			tg3_wait_for_event_ack(tp);  in tg3_timer()
11107 			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,  in tg3_timer()
11109 			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);  in tg3_timer()
11110 			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,  in tg3_timer()
11113 			tg3_generate_fw_event(tp);  in tg3_timer()
11115 		tp->asf_counter = tp->asf_multiplier;  in tg3_timer()
11119 	tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);  in tg3_timer()
11121 	spin_unlock(&tp->lock);  in tg3_timer()
11124 	tp->timer.expires = jiffies + tp->timer_offset;  in tg3_timer()
11125 	add_timer(&tp->timer);  in tg3_timer()
11128 static void tg3_timer_init(struct tg3 *tp)  in tg3_timer_init()  argument
11130 	if (tg3_flag(tp, TAGGED_STATUS) &&  in tg3_timer_init()
11131 	    tg3_asic_rev(tp) != ASIC_REV_5717 &&  in tg3_timer_init()
11132 	    !tg3_flag(tp, 57765_CLASS))  in tg3_timer_init()
11133 		tp->timer_offset = HZ;  in tg3_timer_init()
11135 		tp->timer_offset = HZ / 10;  in tg3_timer_init()
11137 	BUG_ON(tp->timer_offset > HZ);  in tg3_timer_init()
11139 	tp->timer_multiplier = (HZ / tp->timer_offset);  in tg3_timer_init()
11140 	tp->asf_multiplier = (HZ / tp->timer_offset) *  in tg3_timer_init()
11143 	timer_setup(&tp->timer, tg3_timer, 0);  in tg3_timer_init()
11146 static void tg3_timer_start(struct tg3 *tp)  in tg3_timer_start()  argument
11148 	tp->asf_counter   = tp->asf_multiplier;  in tg3_timer_start()
11149 	tp->timer_counter = tp->timer_multiplier;  in tg3_timer_start()
11151 	tp->timer.expires = jiffies + tp->timer_offset;  in tg3_timer_start()
11152 	add_timer(&tp->timer);  in tg3_timer_start()
11155 static void tg3_timer_stop(struct tg3 *tp)  in tg3_timer_stop()  argument
11157 	del_timer_sync(&tp->timer);  in tg3_timer_stop()
11163 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)  in tg3_restart_hw()  argument
11164 	__releases(tp->lock)  in tg3_restart_hw()
11165 	__acquires(tp->lock)  in tg3_restart_hw()
11169 	err = tg3_init_hw(tp, reset_phy);  in tg3_restart_hw()
11171 		netdev_err(tp->dev,  in tg3_restart_hw()
11173 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_restart_hw()
11174 		tg3_full_unlock(tp);  in tg3_restart_hw()
11175 		tg3_timer_stop(tp);  in tg3_restart_hw()
11176 		tp->irq_sync = 0;  in tg3_restart_hw()
11177 		tg3_napi_enable(tp);  in tg3_restart_hw()
11178 		dev_close(tp->dev);  in tg3_restart_hw()
11179 		tg3_full_lock(tp, 0);  in tg3_restart_hw()
11186 	struct tg3 *tp = container_of(work, struct tg3, reset_task);  in tg3_reset_task()  local
11190 	tg3_full_lock(tp, 0);  in tg3_reset_task()
11192 	if (!netif_running(tp->dev)) {  in tg3_reset_task()
11193 		tg3_flag_clear(tp, RESET_TASK_PENDING);  in tg3_reset_task()
11194 		tg3_full_unlock(tp);  in tg3_reset_task()
11199 	tg3_full_unlock(tp);  in tg3_reset_task()
11201 	tg3_phy_stop(tp);  in tg3_reset_task()
11203 	tg3_netif_stop(tp);  in tg3_reset_task()
11205 	tg3_full_lock(tp, 1);  in tg3_reset_task()
11207 	if (tg3_flag(tp, TX_RECOVERY_PENDING)) {  in tg3_reset_task()
11208 		tp->write32_tx_mbox = tg3_write32_tx_mbox;  in tg3_reset_task()
11209 		tp->write32_rx_mbox = tg3_write_flush_reg32;  in tg3_reset_task()
11210 		tg3_flag_set(tp, MBOX_WRITE_REORDER);  in tg3_reset_task()
11211 		tg3_flag_clear(tp, TX_RECOVERY_PENDING);  in tg3_reset_task()
11214 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);  in tg3_reset_task()
11215 	err = tg3_init_hw(tp, true);  in tg3_reset_task()
11219 	tg3_netif_start(tp);  in tg3_reset_task()
11222 	tg3_full_unlock(tp);  in tg3_reset_task()
11225 		tg3_phy_start(tp);  in tg3_reset_task()
11227 	tg3_flag_clear(tp, RESET_TASK_PENDING);  in tg3_reset_task()
11231 static int tg3_request_irq(struct tg3 *tp, int irq_num)  in tg3_request_irq()  argument
11236 	struct tg3_napi *tnapi = &tp->napi[irq_num];  in tg3_request_irq()
11238 	if (tp->irq_cnt == 1)  in tg3_request_irq()
11239 		name = tp->dev->name;  in tg3_request_irq()
11244 				 "%s-txrx-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11247 				 "%s-tx-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11250 				 "%s-rx-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11253 				 "%s-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11257 	if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {  in tg3_request_irq()
11259 		if (tg3_flag(tp, 1SHOT_MSI))  in tg3_request_irq()
11264 		if (tg3_flag(tp, TAGGED_STATUS))  in tg3_request_irq()
11272 static int tg3_test_interrupt(struct tg3 *tp)  in tg3_test_interrupt()  argument
11274 	struct tg3_napi *tnapi = &tp->napi[0];  in tg3_test_interrupt()
11275 	struct net_device *dev = tp->dev;  in tg3_test_interrupt()
11282 	tg3_disable_ints(tp);  in tg3_test_interrupt()
11290 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_test_interrupt()
11301 	tg3_enable_ints(tp);  in tg3_test_interrupt()
11303 	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |  in tg3_test_interrupt()
11318 		if (tg3_flag(tp, 57765_PLUS) &&  in tg3_test_interrupt()
11325 	tg3_disable_ints(tp);  in tg3_test_interrupt()
11329 	err = tg3_request_irq(tp, 0);  in tg3_test_interrupt()
11336 		if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {  in tg3_test_interrupt()
11349 static int tg3_test_msi(struct tg3 *tp)  in tg3_test_msi()  argument
11354 	if (!tg3_flag(tp, USING_MSI))  in tg3_test_msi()
11360 	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_test_msi()
11361 	pci_write_config_word(tp->pdev, PCI_COMMAND,  in tg3_test_msi()
11364 	err = tg3_test_interrupt(tp);  in tg3_test_msi()
11366 	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_test_msi()
11376 	netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "  in tg3_test_msi()
11380 	free_irq(tp->napi[0].irq_vec, &tp->napi[0]);  in tg3_test_msi()
11382 	pci_disable_msi(tp->pdev);  in tg3_test_msi()
11384 	tg3_flag_clear(tp, USING_MSI);  in tg3_test_msi()
11385 	tp->napi[0].irq_vec = tp->pdev->irq;  in tg3_test_msi()
11387 	err = tg3_request_irq(tp, 0);  in tg3_test_msi()
11394 	tg3_full_lock(tp, 1);  in tg3_test_msi()
11396 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_test_msi()
11397 	err = tg3_init_hw(tp, true);  in tg3_test_msi()
11399 	tg3_full_unlock(tp);  in tg3_test_msi()
11402 		free_irq(tp->napi[0].irq_vec, &tp->napi[0]);  in tg3_test_msi()
11407 static int tg3_request_firmware(struct tg3 *tp)  in tg3_request_firmware()  argument
11411 	if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {  in tg3_request_firmware()
11412 		netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",  in tg3_request_firmware()
11413 			   tp->fw_needed);  in tg3_request_firmware()
11417 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_request_firmware()
11424 	tp->fw_len = be32_to_cpu(fw_hdr->len);	/* includes bss */  in tg3_request_firmware()
11425 	if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {  in tg3_request_firmware()
11426 		netdev_err(tp->dev, "bogus length %d in \"%s\"\n",  in tg3_request_firmware()
11427 			   tp->fw_len, tp->fw_needed);  in tg3_request_firmware()
11428 		release_firmware(tp->fw);  in tg3_request_firmware()
11429 		tp->fw = NULL;  in tg3_request_firmware()
11434 	tp->fw_needed = NULL;  in tg3_request_firmware()
11438 static u32 tg3_irq_count(struct tg3 *tp)  in tg3_irq_count()  argument
11440 	u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);  in tg3_irq_count()
11448 		irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);  in tg3_irq_count()
11454 static bool tg3_enable_msix(struct tg3 *tp)  in tg3_enable_msix()  argument
11459 	tp->txq_cnt = tp->txq_req;  in tg3_enable_msix()
11460 	tp->rxq_cnt = tp->rxq_req;  in tg3_enable_msix()
11461 	if (!tp->rxq_cnt)  in tg3_enable_msix()
11462 		tp->rxq_cnt = netif_get_num_default_rss_queues();  in tg3_enable_msix()
11463 	if (tp->rxq_cnt > tp->rxq_max)  in tg3_enable_msix()
11464 		tp->rxq_cnt = tp->rxq_max;  in tg3_enable_msix()
11470 	if (!tp->txq_req)  in tg3_enable_msix()
11471 		tp->txq_cnt = 1;  in tg3_enable_msix()
11473 	tp->irq_cnt = tg3_irq_count(tp);  in tg3_enable_msix()
11475 	for (i = 0; i < tp->irq_max; i++) {  in tg3_enable_msix()
11480 	rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);  in tg3_enable_msix()
11483 	} else if (rc < tp->irq_cnt) {  in tg3_enable_msix()
11484 		netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",  in tg3_enable_msix()
11485 			      tp->irq_cnt, rc);  in tg3_enable_msix()
11486 		tp->irq_cnt = rc;  in tg3_enable_msix()
11487 		tp->rxq_cnt = max(rc - 1, 1);  in tg3_enable_msix()
11488 		if (tp->txq_cnt)  in tg3_enable_msix()
11489 			tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);  in tg3_enable_msix()
11492 	for (i = 0; i < tp->irq_max; i++)  in tg3_enable_msix()
11493 		tp->napi[i].irq_vec = msix_ent[i].vector;  in tg3_enable_msix()
11495 	if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {  in tg3_enable_msix()
11496 		pci_disable_msix(tp->pdev);  in tg3_enable_msix()
11500 	if (tp->irq_cnt == 1)  in tg3_enable_msix()
11503 	tg3_flag_set(tp, ENABLE_RSS);  in tg3_enable_msix()
11505 	if (tp->txq_cnt > 1)  in tg3_enable_msix()
11506 		tg3_flag_set(tp, ENABLE_TSS);  in tg3_enable_msix()
11508 	netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);  in tg3_enable_msix()
11513 static void tg3_ints_init(struct tg3 *tp)  in tg3_ints_init()  argument
11515 	if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&  in tg3_ints_init()
11516 	    !tg3_flag(tp, TAGGED_STATUS)) {  in tg3_ints_init()
11520 		netdev_warn(tp->dev,  in tg3_ints_init()
11525 	if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))  in tg3_ints_init()
11526 		tg3_flag_set(tp, USING_MSIX);  in tg3_ints_init()
11527 	else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)  in tg3_ints_init()
11528 		tg3_flag_set(tp, USING_MSI);  in tg3_ints_init()
11530 	if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {  in tg3_ints_init()
11532 		if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)  in tg3_ints_init()
11534 		if (!tg3_flag(tp, 1SHOT_MSI))  in tg3_ints_init()
11539 	if (!tg3_flag(tp, USING_MSIX)) {  in tg3_ints_init()
11540 		tp->irq_cnt = 1;  in tg3_ints_init()
11541 		tp->napi[0].irq_vec = tp->pdev->irq;  in tg3_ints_init()
11544 	if (tp->irq_cnt == 1) {  in tg3_ints_init()
11545 		tp->txq_cnt = 1;  in tg3_ints_init()
11546 		tp->rxq_cnt = 1;  in tg3_ints_init()
11547 		netif_set_real_num_tx_queues(tp->dev, 1);  in tg3_ints_init()
11548 		netif_set_real_num_rx_queues(tp->dev, 1);  in tg3_ints_init()
11552 static void tg3_ints_fini(struct tg3 *tp)  in tg3_ints_fini()  argument
11554 	if (tg3_flag(tp, USING_MSIX))  in tg3_ints_fini()
11555 		pci_disable_msix(tp->pdev);  in tg3_ints_fini()
11556 	else if (tg3_flag(tp, USING_MSI))  in tg3_ints_fini()
11557 		pci_disable_msi(tp->pdev);  in tg3_ints_fini()
11558 	tg3_flag_clear(tp, USING_MSI);  in tg3_ints_fini()
11559 	tg3_flag_clear(tp, USING_MSIX);  in tg3_ints_fini()
11560 	tg3_flag_clear(tp, ENABLE_RSS);  in tg3_ints_fini()
11561 	tg3_flag_clear(tp, ENABLE_TSS);  in tg3_ints_fini()
11564 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,  in tg3_start()  argument
11567 	struct net_device *dev = tp->dev;  in tg3_start()
11574 	tg3_ints_init(tp);  in tg3_start()
11576 	tg3_rss_check_indir_tbl(tp);  in tg3_start()
11581 	err = tg3_alloc_consistent(tp);  in tg3_start()
11585 	tg3_napi_init(tp);  in tg3_start()
11587 	tg3_napi_enable(tp);  in tg3_start()
11589 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_start()
11590 		err = tg3_request_irq(tp, i);  in tg3_start()
11593 				struct tg3_napi *tnapi = &tp->napi[i];  in tg3_start()
11601 	tg3_full_lock(tp, 0);  in tg3_start()
11604 		tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_start()
11606 	err = tg3_init_hw(tp, reset_phy);  in tg3_start()
11608 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_start()
11609 		tg3_free_rings(tp);  in tg3_start()
11612 	tg3_full_unlock(tp);  in tg3_start()
11617 	if (test_irq && tg3_flag(tp, USING_MSI)) {  in tg3_start()
11618 		err = tg3_test_msi(tp);  in tg3_start()
11621 			tg3_full_lock(tp, 0);  in tg3_start()
11622 			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_start()
11623 			tg3_free_rings(tp);  in tg3_start()
11624 			tg3_full_unlock(tp);  in tg3_start()
11629 		if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {  in tg3_start()
11637 	tg3_phy_start(tp);  in tg3_start()
11639 	tg3_hwmon_open(tp);  in tg3_start()
11641 	tg3_full_lock(tp, 0);  in tg3_start()
11643 	tg3_timer_start(tp);  in tg3_start()
11644 	tg3_flag_set(tp, INIT_COMPLETE);  in tg3_start()
11645 	tg3_enable_ints(tp);  in tg3_start()
11647 	tg3_ptp_resume(tp);  in tg3_start()
11649 	tg3_full_unlock(tp);  in tg3_start()
11663 	for (i = tp->irq_cnt - 1; i >= 0; i--) {  in tg3_start()
11664 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_start()
11669 	tg3_napi_disable(tp);  in tg3_start()
11670 	tg3_napi_fini(tp);  in tg3_start()
11671 	tg3_free_consistent(tp);  in tg3_start()
11674 	tg3_ints_fini(tp);  in tg3_start()
11679 static void tg3_stop(struct tg3 *tp)  in tg3_stop()  argument
11683 	tg3_reset_task_cancel(tp);  in tg3_stop()
11684 	tg3_netif_stop(tp);  in tg3_stop()
11686 	tg3_timer_stop(tp);  in tg3_stop()
11688 	tg3_hwmon_close(tp);  in tg3_stop()
11690 	tg3_phy_stop(tp);  in tg3_stop()
11692 	tg3_full_lock(tp, 1);  in tg3_stop()
11694 	tg3_disable_ints(tp);  in tg3_stop()
11696 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_stop()
11697 	tg3_free_rings(tp);  in tg3_stop()
11698 	tg3_flag_clear(tp, INIT_COMPLETE);  in tg3_stop()
11700 	tg3_full_unlock(tp);  in tg3_stop()
11702 	for (i = tp->irq_cnt - 1; i >= 0; i--) {  in tg3_stop()
11703 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_stop()
11707 	tg3_ints_fini(tp);  in tg3_stop()
11709 	tg3_napi_fini(tp);  in tg3_stop()
11711 	tg3_free_consistent(tp);  in tg3_stop()
11716 	struct tg3 *tp = netdev_priv(dev);  in tg3_open()  local
11719 	if (tp->pcierr_recovery) {  in tg3_open()
11725 	if (tp->fw_needed) {  in tg3_open()
11726 		err = tg3_request_firmware(tp);  in tg3_open()
11727 		if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_open()
11729 				netdev_warn(tp->dev, "EEE capability disabled\n");  in tg3_open()
11730 				tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;  in tg3_open()
11731 			} else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {  in tg3_open()
11732 				netdev_warn(tp->dev, "EEE capability restored\n");  in tg3_open()
11733 				tp->phy_flags |= TG3_PHYFLG_EEE_CAP;  in tg3_open()
11735 		} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {  in tg3_open()
11739 			netdev_warn(tp->dev, "TSO capability disabled\n");  in tg3_open()
11740 			tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_open()
11741 		} else if (!tg3_flag(tp, TSO_CAPABLE)) {  in tg3_open()
11742 			netdev_notice(tp->dev, "TSO capability restored\n");  in tg3_open()
11743 			tg3_flag_set(tp, TSO_CAPABLE);  in tg3_open()
11747 	tg3_carrier_off(tp);  in tg3_open()
11749 	err = tg3_power_up(tp);  in tg3_open()
11753 	tg3_full_lock(tp, 0);  in tg3_open()
11755 	tg3_disable_ints(tp);  in tg3_open()
11756 	tg3_flag_clear(tp, INIT_COMPLETE);  in tg3_open()
11758 	tg3_full_unlock(tp);  in tg3_open()
11760 	err = tg3_start(tp,  in tg3_open()
11761 			!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),  in tg3_open()
11764 		tg3_frob_aux_power(tp, false);  in tg3_open()
11765 		pci_set_power_state(tp->pdev, PCI_D3hot);  in tg3_open()
11773 	struct tg3 *tp = netdev_priv(dev);  in tg3_close()  local
11775 	if (tp->pcierr_recovery) {  in tg3_close()
11781 	tg3_stop(tp);  in tg3_close()
11783 	if (pci_device_is_present(tp->pdev)) {  in tg3_close()
11784 		tg3_power_down_prepare(tp);  in tg3_close()
11786 		tg3_carrier_off(tp);  in tg3_close()
11796 static u64 tg3_calc_crc_errors(struct tg3 *tp)  in tg3_calc_crc_errors()  argument
11798 	struct tg3_hw_stats *hw_stats = tp->hw_stats;  in tg3_calc_crc_errors()
11800 	if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_calc_crc_errors()
11801 	    (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_calc_crc_errors()
11802 	     tg3_asic_rev(tp) == ASIC_REV_5701)) {  in tg3_calc_crc_errors()
11805 		if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {  in tg3_calc_crc_errors()
11806 			tg3_writephy(tp, MII_TG3_TEST1,  in tg3_calc_crc_errors()
11808 			tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);  in tg3_calc_crc_errors()
11812 		tp->phy_crc_errors += val;  in tg3_calc_crc_errors()
11814 		return tp->phy_crc_errors;  in tg3_calc_crc_errors()
11824 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)  in tg3_get_estats()  argument
11826 	struct tg3_ethtool_stats *old_estats = &tp->estats_prev;  in tg3_get_estats()
11827 	struct tg3_hw_stats *hw_stats = tp->hw_stats;  in tg3_get_estats()
11908 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)  in tg3_get_nstats()  argument
11910 	struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;  in tg3_get_nstats()
11911 	struct tg3_hw_stats *hw_stats = tp->hw_stats;  in tg3_get_nstats()
11953 		tg3_calc_crc_errors(tp);  in tg3_get_nstats()
11958 	stats->rx_dropped = tp->rx_dropped;  in tg3_get_nstats()
11959 	stats->tx_dropped = tp->tx_dropped;  in tg3_get_nstats()
11970 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_regs()  local
11976 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)  in tg3_get_regs()
11979 	tg3_full_lock(tp, 0);  in tg3_get_regs()
11981 	tg3_dump_legacy_regs(tp, (u32 *)_p);  in tg3_get_regs()
11983 	tg3_full_unlock(tp);  in tg3_get_regs()
11988 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_eeprom_len()  local
11990 	return tp->nvram_size;  in tg3_get_eeprom_len()
11995 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_eeprom()  local
12001 	if (tg3_flag(tp, NO_NVRAM))  in tg3_get_eeprom()
12011 	if (tg3_flag(tp, CPMU_PRESENT)) {  in tg3_get_eeprom()
12021 	tg3_override_clk(tp);  in tg3_get_eeprom()
12031 		ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);  in tg3_get_eeprom()
12043 		ret = tg3_nvram_read_be32(tp, offset + i, &val);  in tg3_get_eeprom()
12067 		ret = tg3_nvram_read_be32(tp, b_offset, &val);  in tg3_get_eeprom()
12077 	tg3_restore_clk(tp);  in tg3_get_eeprom()
12086 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_eeprom()  local
12092 	if (tg3_flag(tp, NO_NVRAM) ||  in tg3_set_eeprom()
12101 		ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);  in tg3_set_eeprom()
12115 		ret = tg3_nvram_read_be32(tp, offset+len-4, &end);  in tg3_set_eeprom()
12132 	ret = tg3_nvram_write_block(tp, offset, len, buf);  in tg3_set_eeprom()
12143 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_link_ksettings()  local
12146 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_get_link_ksettings()
12148 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_get_link_ksettings()
12150 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_get_link_ksettings()
12158 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))  in tg3_get_link_ksettings()
12162 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_get_link_ksettings()
12176 	advertising = tp->link_config.advertising;  in tg3_get_link_ksettings()
12177 	if (tg3_flag(tp, PAUSE_AUTONEG)) {  in tg3_get_link_ksettings()
12178 		if (tp->link_config.flowctrl & FLOW_CTRL_RX) {  in tg3_get_link_ksettings()
12179 			if (tp->link_config.flowctrl & FLOW_CTRL_TX) {  in tg3_get_link_ksettings()
12185 		} else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {  in tg3_get_link_ksettings()
12192 	if (netif_running(dev) && tp->link_up) {  in tg3_get_link_ksettings()
12193 		cmd->base.speed = tp->link_config.active_speed;  in tg3_get_link_ksettings()
12194 		cmd->base.duplex = tp->link_config.active_duplex;  in tg3_get_link_ksettings()
12197 			tp->link_config.rmt_adv);  in tg3_get_link_ksettings()
12199 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_get_link_ksettings()
12200 			if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)  in tg3_get_link_ksettings()
12210 	cmd->base.phy_address = tp->phy_addr;  in tg3_get_link_ksettings()
12211 	cmd->base.autoneg = tp->link_config.autoneg;  in tg3_get_link_ksettings()
12218 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_link_ksettings()  local
12222 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_set_link_ksettings()
12224 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_set_link_ksettings()
12226 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_set_link_ksettings()
12247 		if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))  in tg3_set_link_ksettings()
12251 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_set_link_ksettings()
12272 		if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {  in tg3_set_link_ksettings()
12285 	tg3_full_lock(tp, 0);  in tg3_set_link_ksettings()
12287 	tp->link_config.autoneg = cmd->base.autoneg;  in tg3_set_link_ksettings()
12289 		tp->link_config.advertising = (advertising |  in tg3_set_link_ksettings()
12291 		tp->link_config.speed = SPEED_UNKNOWN;  in tg3_set_link_ksettings()
12292 		tp->link_config.duplex = DUPLEX_UNKNOWN;  in tg3_set_link_ksettings()
12294 		tp->link_config.advertising = 0;  in tg3_set_link_ksettings()
12295 		tp->link_config.speed = speed;  in tg3_set_link_ksettings()
12296 		tp->link_config.duplex = cmd->base.duplex;  in tg3_set_link_ksettings()
12299 	tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_set_link_ksettings()
12301 	tg3_warn_mgmt_link_flap(tp);  in tg3_set_link_ksettings()
12304 		tg3_setup_phy(tp, true);  in tg3_set_link_ksettings()
12306 	tg3_full_unlock(tp);  in tg3_set_link_ksettings()
12313 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_drvinfo()  local
12317 	strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));  in tg3_get_drvinfo()
12318 	strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));  in tg3_get_drvinfo()
12323 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_wol()  local
12325 	if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))  in tg3_get_wol()
12330 	if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))  in tg3_get_wol()
12337 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_wol()  local
12338 	struct device *dp = &tp->pdev->dev;  in tg3_set_wol()
12343 	    !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))  in tg3_set_wol()
12349 		tg3_flag_set(tp, WOL_ENABLE);  in tg3_set_wol()
12351 		tg3_flag_clear(tp, WOL_ENABLE);  in tg3_set_wol()
12358 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_msglevel()  local
12359 	return tp->msg_enable;  in tg3_get_msglevel()
12364 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_msglevel()  local
12365 	tp->msg_enable = value;  in tg3_set_msglevel()
12370 	struct tg3 *tp = netdev_priv(dev);  in tg3_nway_reset()  local
12376 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_nway_reset()
12379 	tg3_warn_mgmt_link_flap(tp);  in tg3_nway_reset()
12381 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_nway_reset()
12382 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_nway_reset()
12384 		r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_nway_reset()
12388 		spin_lock_bh(&tp->lock);  in tg3_nway_reset()
12390 		tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_nway_reset()
12391 		if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&  in tg3_nway_reset()
12393 		     (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {  in tg3_nway_reset()
12394 			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |  in tg3_nway_reset()
12398 		spin_unlock_bh(&tp->lock);  in tg3_nway_reset()
12406 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_ringparam()  local
12408 	ering->rx_max_pending = tp->rx_std_ring_mask;  in tg3_get_ringparam()
12409 	if (tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_get_ringparam()
12410 		ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;  in tg3_get_ringparam()
12416 	ering->rx_pending = tp->rx_pending;  in tg3_get_ringparam()
12417 	if (tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_get_ringparam()
12418 		ering->rx_jumbo_pending = tp->rx_jumbo_pending;  in tg3_get_ringparam()
12422 	ering->tx_pending = tp->napi[0].tx_pending;  in tg3_get_ringparam()
12427 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_ringparam()  local
12430 	if ((ering->rx_pending > tp->rx_std_ring_mask) ||  in tg3_set_ringparam()
12431 	    (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||  in tg3_set_ringparam()
12434 	    (tg3_flag(tp, TSO_BUG) &&  in tg3_set_ringparam()
12439 		tg3_phy_stop(tp);  in tg3_set_ringparam()
12440 		tg3_netif_stop(tp);  in tg3_set_ringparam()
12444 	tg3_full_lock(tp, irq_sync);  in tg3_set_ringparam()
12446 	tp->rx_pending = ering->rx_pending;  in tg3_set_ringparam()
12448 	if (tg3_flag(tp, MAX_RXPEND_64) &&  in tg3_set_ringparam()
12449 	    tp->rx_pending > 63)  in tg3_set_ringparam()
12450 		tp->rx_pending = 63;  in tg3_set_ringparam()
12452 	if (tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_set_ringparam()
12453 		tp->rx_jumbo_pending = ering->rx_jumbo_pending;  in tg3_set_ringparam()
12455 	for (i = 0; i < tp->irq_max; i++)  in tg3_set_ringparam()
12456 		tp->napi[i].tx_pending = ering->tx_pending;  in tg3_set_ringparam()
12459 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_set_ringparam()
12460 		err = tg3_restart_hw(tp, false);  in tg3_set_ringparam()
12462 			tg3_netif_start(tp);  in tg3_set_ringparam()
12465 	tg3_full_unlock(tp);  in tg3_set_ringparam()
12468 		tg3_phy_start(tp);  in tg3_set_ringparam()
12475 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_pauseparam()  local
12477 	epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);  in tg3_get_pauseparam()
12479 	if (tp->link_config.flowctrl & FLOW_CTRL_RX)  in tg3_get_pauseparam()
12484 	if (tp->link_config.flowctrl & FLOW_CTRL_TX)  in tg3_get_pauseparam()
12492 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_pauseparam()  local
12495 	if (tp->link_config.autoneg == AUTONEG_ENABLE)  in tg3_set_pauseparam()
12496 		tg3_warn_mgmt_link_flap(tp);  in tg3_set_pauseparam()
12498 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_set_pauseparam()
12502 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_set_pauseparam()
12509 		tp->link_config.flowctrl = 0;  in tg3_set_pauseparam()
12511 			tp->link_config.flowctrl |= FLOW_CTRL_RX;  in tg3_set_pauseparam()
12514 				tp->link_config.flowctrl |= FLOW_CTRL_TX;  in tg3_set_pauseparam()
12520 			tp->link_config.flowctrl |= FLOW_CTRL_TX;  in tg3_set_pauseparam()
12526 			tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12528 			tg3_flag_clear(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12530 		if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {  in tg3_set_pauseparam()
12552 				tg3_setup_flow_control(tp, 0, 0);  in tg3_set_pauseparam()
12554 			tp->link_config.advertising &=  in tg3_set_pauseparam()
12557 			tp->link_config.advertising |= newadv;  in tg3_set_pauseparam()
12563 			tg3_netif_stop(tp);  in tg3_set_pauseparam()
12567 		tg3_full_lock(tp, irq_sync);  in tg3_set_pauseparam()
12570 			tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12572 			tg3_flag_clear(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12574 			tp->link_config.flowctrl |= FLOW_CTRL_RX;  in tg3_set_pauseparam()
12576 			tp->link_config.flowctrl &= ~FLOW_CTRL_RX;  in tg3_set_pauseparam()
12578 			tp->link_config.flowctrl |= FLOW_CTRL_TX;  in tg3_set_pauseparam()
12580 			tp->link_config.flowctrl &= ~FLOW_CTRL_TX;  in tg3_set_pauseparam()
12583 			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_set_pauseparam()
12584 			err = tg3_restart_hw(tp, false);  in tg3_set_pauseparam()
12586 				tg3_netif_start(tp);  in tg3_set_pauseparam()
12589 		tg3_full_unlock(tp);  in tg3_set_pauseparam()
12592 	tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_set_pauseparam()
12612 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_rxnfc()  local
12614 	if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_get_rxnfc()
12619 		if (netif_running(tp->dev))  in tg3_get_rxnfc()
12620 			info->data = tp->rxq_cnt;  in tg3_get_rxnfc()
12637 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_rxfh_indir_size()  local
12639 	if (tg3_flag(tp, SUPPORT_MSIX))  in tg3_get_rxfh_indir_size()
12647 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_rxfh()  local
12656 		indir[i] = tp->rss_ind_tbl[i];  in tg3_get_rxfh()
12664 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_rxfh()  local
12678 		tp->rss_ind_tbl[i] = indir[i];  in tg3_set_rxfh()
12680 	if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))  in tg3_set_rxfh()
12686 	tg3_full_lock(tp, 0);  in tg3_set_rxfh()
12687 	tg3_rss_write_indir_tbl(tp);  in tg3_set_rxfh()
12688 	tg3_full_unlock(tp);  in tg3_set_rxfh()
12696 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_channels()  local
12699 	channel->max_rx = tp->rxq_max;  in tg3_get_channels()
12700 	channel->max_tx = tp->txq_max;  in tg3_get_channels()
12703 		channel->rx_count = tp->rxq_cnt;  in tg3_get_channels()
12704 		channel->tx_count = tp->txq_cnt;  in tg3_get_channels()
12706 		if (tp->rxq_req)  in tg3_get_channels()
12707 			channel->rx_count = tp->rxq_req;  in tg3_get_channels()
12709 			channel->rx_count = min(deflt_qs, tp->rxq_max);  in tg3_get_channels()
12711 		if (tp->txq_req)  in tg3_get_channels()
12712 			channel->tx_count = tp->txq_req;  in tg3_get_channels()
12714 			channel->tx_count = min(deflt_qs, tp->txq_max);  in tg3_get_channels()
12721 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_channels()  local
12723 	if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_set_channels()
12726 	if (channel->rx_count > tp->rxq_max ||  in tg3_set_channels()
12727 	    channel->tx_count > tp->txq_max)  in tg3_set_channels()
12730 	tp->rxq_req = channel->rx_count;  in tg3_set_channels()
12731 	tp->txq_req = channel->tx_count;  in tg3_set_channels()
12736 	tg3_stop(tp);  in tg3_set_channels()
12738 	tg3_carrier_off(tp);  in tg3_set_channels()
12740 	tg3_start(tp, true, false, false);  in tg3_set_channels()
12763 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_phys_id()  local
12765 	if (!netif_running(tp->dev))  in tg3_set_phys_id()
12788 		tw32(MAC_LED_CTRL, tp->led_ctrl);  in tg3_set_phys_id()
12798 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_ethtool_stats()  local
12800 	if (tp->hw_stats)  in tg3_get_ethtool_stats()
12801 		tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);  in tg3_get_ethtool_stats()
12806 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)  in tg3_vpd_readblock()  argument
12813 	if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))  in tg3_vpd_readblock()
12820 			if (tg3_nvram_read(tp, offset, &val))  in tg3_vpd_readblock()
12830 			if (tg3_nvram_read(tp, offset + 4, &offset))  in tg3_vpd_readblock()
12833 			offset = tg3_nvram_logical_addr(tp, offset);  in tg3_vpd_readblock()
12852 			if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))  in tg3_vpd_readblock()
12862 			cnt = pci_read_vpd(tp->pdev, pos,  in tg3_vpd_readblock()
12892 static int tg3_test_nvram(struct tg3 *tp)  in tg3_test_nvram()  argument
12898 	if (tg3_flag(tp, NO_NVRAM))  in tg3_test_nvram()
12901 	if (tg3_nvram_read(tp, 0, &magic) != 0)  in tg3_test_nvram()
12944 		err = tg3_nvram_read_be32(tp, i, &buf[j]);  in tg3_test_nvram()
13035 	buf = tg3_vpd_readblock(tp, &len);  in tg3_test_nvram()
13074 static int tg3_test_link(struct tg3 *tp)  in tg3_test_link()  argument
13078 	if (!netif_running(tp->dev))  in tg3_test_link()
13081 	if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_test_link()
13087 		if (tp->link_up)  in tg3_test_link()
13098 static int tg3_test_registers(struct tg3 *tp)  in tg3_test_registers()  argument
13248 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_test_registers()
13250 		if (tg3_flag(tp, 5750_PLUS))  in tg3_test_registers()
13261 		if (tg3_flag(tp, IS_5788) &&  in tg3_test_registers()
13311 	if (netif_msg_hw(tp))  in tg3_test_registers()
13312 		netdev_err(tp->dev,  in tg3_test_registers()
13318 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)  in tg3_do_mem_test()  argument
13328 			tg3_write_mem(tp, offset + j, test_pattern[i]);  in tg3_do_mem_test()
13329 			tg3_read_mem(tp, offset + j, &val);  in tg3_do_mem_test()
13337 static int tg3_test_memory(struct tg3 *tp)  in tg3_test_memory()  argument
13384 	if (tg3_flag(tp, 5717_PLUS))  in tg3_test_memory()
13386 	else if (tg3_flag(tp, 57765_CLASS) ||  in tg3_test_memory()
13387 		 tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_test_memory()
13389 	else if (tg3_flag(tp, 5755_PLUS))  in tg3_test_memory()
13391 	else if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_test_memory()
13393 	else if (tg3_flag(tp, 5705_PLUS))  in tg3_test_memory()
13399 		err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);  in tg3_test_memory()
13430 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)  in tg3_run_loopback()  argument
13441 	struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;  in tg3_run_loopback()
13443 	tnapi = &tp->napi[0];  in tg3_run_loopback()
13444 	rnapi = &tp->napi[0];  in tg3_run_loopback()
13445 	if (tp->irq_cnt > 1) {  in tg3_run_loopback()
13446 		if (tg3_flag(tp, ENABLE_RSS))  in tg3_run_loopback()
13447 			rnapi = &tp->napi[1];  in tg3_run_loopback()
13448 		if (tg3_flag(tp, ENABLE_TSS))  in tg3_run_loopback()
13449 			tnapi = &tp->napi[1];  in tg3_run_loopback()
13456 	skb = netdev_alloc_skb(tp->dev, tx_len);  in tg3_run_loopback()
13461 	memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);  in tg3_run_loopback()
13485 		if (tg3_flag(tp, HW_TSO_1) ||  in tg3_run_loopback()
13486 		    tg3_flag(tp, HW_TSO_2) ||  in tg3_run_loopback()
13487 		    tg3_flag(tp, HW_TSO_3)) {  in tg3_run_loopback()
13495 		if (tg3_flag(tp, HW_TSO_3)) {  in tg3_run_loopback()
13500 		} else if (tg3_flag(tp, HW_TSO_2))  in tg3_run_loopback()
13502 		else if (tg3_flag(tp, HW_TSO_1) ||  in tg3_run_loopback()
13503 			 tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_run_loopback()
13514 		if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&  in tg3_run_loopback()
13522 	map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);  in tg3_run_loopback()
13523 	if (pci_dma_mapping_error(tp->pdev, map)) {  in tg3_run_loopback()
13532 	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |  in tg3_run_loopback()
13559 		tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |  in tg3_run_loopback()
13621 		pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,  in tg3_run_loopback()
13624 		rx_data += TG3_RX_OFFSET(tp);  in tg3_run_loopback()
13646 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)  in tg3_test_loopback()  argument
13652 	if (tp->dma_limit)  in tg3_test_loopback()
13653 		jmb_pkt_sz = tp->dma_limit - ETH_HLEN;  in tg3_test_loopback()
13655 	eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;  in tg3_test_loopback()
13656 	tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;  in tg3_test_loopback()
13658 	if (!netif_running(tp->dev)) {  in tg3_test_loopback()
13666 	err = tg3_reset_hw(tp, true);  in tg3_test_loopback()
13675 	if (tg3_flag(tp, ENABLE_RSS)) {  in tg3_test_loopback()
13689 	if (tg3_asic_rev(tp) != ASIC_REV_5780 &&  in tg3_test_loopback()
13690 	    !tg3_flag(tp, CPMU_PRESENT)) {  in tg3_test_loopback()
13691 		tg3_mac_loopback(tp, true);  in tg3_test_loopback()
13693 		if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))  in tg3_test_loopback()
13696 		if (tg3_flag(tp, JUMBO_RING_ENABLE) &&  in tg3_test_loopback()
13697 		    tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))  in tg3_test_loopback()
13700 		tg3_mac_loopback(tp, false);  in tg3_test_loopback()
13703 	if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_test_loopback()
13704 	    !tg3_flag(tp, USE_PHYLIB)) {  in tg3_test_loopback()
13707 		tg3_phy_lpbk_set(tp, 0, false);  in tg3_test_loopback()
13716 		if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))  in tg3_test_loopback()
13718 		if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_test_loopback()
13719 		    tg3_run_loopback(tp, ETH_FRAME_LEN, true))  in tg3_test_loopback()
13721 		if (tg3_flag(tp, JUMBO_RING_ENABLE) &&  in tg3_test_loopback()
13722 		    tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))  in tg3_test_loopback()
13726 			tg3_phy_lpbk_set(tp, 0, true);  in tg3_test_loopback()
13734 			if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))  in tg3_test_loopback()
13737 			if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_test_loopback()
13738 			    tg3_run_loopback(tp, ETH_FRAME_LEN, true))  in tg3_test_loopback()
13741 			if (tg3_flag(tp, JUMBO_RING_ENABLE) &&  in tg3_test_loopback()
13742 			    tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))  in tg3_test_loopback()
13748 		if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)  in tg3_test_loopback()
13749 			tg3_phy_toggle_apd(tp, true);  in tg3_test_loopback()
13756 	tp->phy_flags |= eee_cap;  in tg3_test_loopback()
13764 	struct tg3 *tp = netdev_priv(dev);  in tg3_self_test()  local
13767 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {  in tg3_self_test()
13768 		if (tg3_power_up(tp)) {  in tg3_self_test()
13773 		tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_self_test()
13778 	if (tg3_test_nvram(tp) != 0) {  in tg3_self_test()
13782 	if (!doextlpbk && tg3_test_link(tp)) {  in tg3_self_test()
13790 			tg3_phy_stop(tp);  in tg3_self_test()
13791 			tg3_netif_stop(tp);  in tg3_self_test()
13795 		tg3_full_lock(tp, irq_sync);  in tg3_self_test()
13796 		tg3_halt(tp, RESET_KIND_SUSPEND, 1);  in tg3_self_test()
13797 		err = tg3_nvram_lock(tp);  in tg3_self_test()
13798 		tg3_halt_cpu(tp, RX_CPU_BASE);  in tg3_self_test()
13799 		if (!tg3_flag(tp, 5705_PLUS))  in tg3_self_test()
13800 			tg3_halt_cpu(tp, TX_CPU_BASE);  in tg3_self_test()
13802 			tg3_nvram_unlock(tp);  in tg3_self_test()
13804 		if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_self_test()
13805 			tg3_phy_reset(tp);  in tg3_self_test()
13807 		if (tg3_test_registers(tp) != 0) {  in tg3_self_test()
13812 		if (tg3_test_memory(tp) != 0) {  in tg3_self_test()
13820 		if (tg3_test_loopback(tp, data, doextlpbk))  in tg3_self_test()
13823 		tg3_full_unlock(tp);  in tg3_self_test()
13825 		if (tg3_test_interrupt(tp) != 0) {  in tg3_self_test()
13830 		tg3_full_lock(tp, 0);  in tg3_self_test()
13832 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_self_test()
13834 			tg3_flag_set(tp, INIT_COMPLETE);  in tg3_self_test()
13835 			err2 = tg3_restart_hw(tp, true);  in tg3_self_test()
13837 				tg3_netif_start(tp);  in tg3_self_test()
13840 		tg3_full_unlock(tp);  in tg3_self_test()
13843 			tg3_phy_start(tp);  in tg3_self_test()
13845 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)  in tg3_self_test()
13846 		tg3_power_down_prepare(tp);  in tg3_self_test()
13852 	struct tg3 *tp = netdev_priv(dev);  in tg3_hwtstamp_set()  local
13855 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_hwtstamp_set()
13870 		tp->rxptpctl = 0;  in tg3_hwtstamp_set()
13873 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |  in tg3_hwtstamp_set()
13877 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |  in tg3_hwtstamp_set()
13881 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |  in tg3_hwtstamp_set()
13885 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |  in tg3_hwtstamp_set()
13889 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |  in tg3_hwtstamp_set()
13893 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |  in tg3_hwtstamp_set()
13897 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |  in tg3_hwtstamp_set()
13901 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |  in tg3_hwtstamp_set()
13905 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |  in tg3_hwtstamp_set()
13909 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |  in tg3_hwtstamp_set()
13913 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |  in tg3_hwtstamp_set()
13917 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |  in tg3_hwtstamp_set()
13924 	if (netif_running(dev) && tp->rxptpctl)  in tg3_hwtstamp_set()
13926 		     tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);  in tg3_hwtstamp_set()
13929 		tg3_flag_set(tp, TX_TSTAMP_EN);  in tg3_hwtstamp_set()
13931 		tg3_flag_clear(tp, TX_TSTAMP_EN);  in tg3_hwtstamp_set()
13939 	struct tg3 *tp = netdev_priv(dev);  in tg3_hwtstamp_get()  local
13942 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_hwtstamp_get()
13946 	stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?  in tg3_hwtstamp_get()
13949 	switch (tp->rxptpctl) {  in tg3_hwtstamp_get()
14001 	struct tg3 *tp = netdev_priv(dev);  in tg3_ioctl()  local
14004 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_ioctl()
14006 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_ioctl()
14008 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_ioctl()
14014 		data->phy_id = tp->phy_addr;  in tg3_ioctl()
14020 		if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_ioctl()
14026 		spin_lock_bh(&tp->lock);  in tg3_ioctl()
14027 		err = __tg3_readphy(tp, data->phy_id & 0x1f,  in tg3_ioctl()
14029 		spin_unlock_bh(&tp->lock);  in tg3_ioctl()
14037 		if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_ioctl()
14043 		spin_lock_bh(&tp->lock);  in tg3_ioctl()
14044 		err = __tg3_writephy(tp, data->phy_id & 0x1f,  in tg3_ioctl()
14046 		spin_unlock_bh(&tp->lock);  in tg3_ioctl()
14065 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_coalesce()  local
14067 	memcpy(ec, &tp->coal, sizeof(*ec));  in tg3_get_coalesce()
14073 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_coalesce()  local
14077 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_set_coalesce()
14099 	tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;  in tg3_set_coalesce()
14100 	tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;  in tg3_set_coalesce()
14101 	tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;  in tg3_set_coalesce()
14102 	tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;  in tg3_set_coalesce()
14103 	tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;  in tg3_set_coalesce()
14104 	tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;  in tg3_set_coalesce()
14105 	tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;  in tg3_set_coalesce()
14106 	tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;  in tg3_set_coalesce()
14107 	tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;  in tg3_set_coalesce()
14110 		tg3_full_lock(tp, 0);  in tg3_set_coalesce()
14111 		__tg3_set_coalesce(tp, &tp->coal);  in tg3_set_coalesce()
14112 		tg3_full_unlock(tp);  in tg3_set_coalesce()
14119 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_eee()  local
14121 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {  in tg3_set_eee()
14122 		netdev_warn(tp->dev, "Board does not support EEE!\n");  in tg3_set_eee()
14126 	if (edata->advertised != tp->eee.advertised) {  in tg3_set_eee()
14127 		netdev_warn(tp->dev,  in tg3_set_eee()
14133 		netdev_warn(tp->dev,  in tg3_set_eee()
14139 	tp->eee = *edata;  in tg3_set_eee()
14141 	tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_set_eee()
14142 	tg3_warn_mgmt_link_flap(tp);  in tg3_set_eee()
14144 	if (netif_running(tp->dev)) {  in tg3_set_eee()
14145 		tg3_full_lock(tp, 0);  in tg3_set_eee()
14146 		tg3_setup_eee(tp);  in tg3_set_eee()
14147 		tg3_phy_reset(tp);  in tg3_set_eee()
14148 		tg3_full_unlock(tp);  in tg3_set_eee()
14156 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_eee()  local
14158 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {  in tg3_get_eee()
14159 		netdev_warn(tp->dev,  in tg3_get_eee()
14164 	*edata = tp->eee;  in tg3_get_eee()
14208 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_stats64()  local
14210 	spin_lock_bh(&tp->lock);  in tg3_get_stats64()
14211 	if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {  in tg3_get_stats64()
14212 		*stats = tp->net_stats_prev;  in tg3_get_stats64()
14213 		spin_unlock_bh(&tp->lock);  in tg3_get_stats64()
14217 	tg3_get_nstats(tp, stats);  in tg3_get_stats64()
14218 	spin_unlock_bh(&tp->lock);  in tg3_get_stats64()
14223 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_rx_mode()  local
14228 	tg3_full_lock(tp, 0);  in tg3_set_rx_mode()
14230 	tg3_full_unlock(tp);  in tg3_set_rx_mode()
14233 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,  in tg3_set_mtu()  argument
14239 		if (tg3_flag(tp, 5780_CLASS)) {  in tg3_set_mtu()
14241 			tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_set_mtu()
14243 			tg3_flag_set(tp, JUMBO_RING_ENABLE);  in tg3_set_mtu()
14246 		if (tg3_flag(tp, 5780_CLASS)) {  in tg3_set_mtu()
14247 			tg3_flag_set(tp, TSO_CAPABLE);  in tg3_set_mtu()
14250 		tg3_flag_clear(tp, JUMBO_RING_ENABLE);  in tg3_set_mtu()
14256 	struct tg3 *tp = netdev_priv(dev);  in tg3_change_mtu()  local
14264 		tg3_set_mtu(dev, tp, new_mtu);  in tg3_change_mtu()
14268 	tg3_phy_stop(tp);  in tg3_change_mtu()
14270 	tg3_netif_stop(tp);  in tg3_change_mtu()
14272 	tg3_set_mtu(dev, tp, new_mtu);  in tg3_change_mtu()
14274 	tg3_full_lock(tp, 1);  in tg3_change_mtu()
14276 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_change_mtu()
14281 	if (tg3_asic_rev(tp) == ASIC_REV_57766 ||  in tg3_change_mtu()
14282 	    tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_change_mtu()
14283 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_change_mtu()
14284 	    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_change_mtu()
14287 	err = tg3_restart_hw(tp, reset_phy);  in tg3_change_mtu()
14290 		tg3_netif_start(tp);  in tg3_change_mtu()
14292 	tg3_full_unlock(tp);  in tg3_change_mtu()
14295 		tg3_phy_start(tp);  in tg3_change_mtu()
14318 static void tg3_get_eeprom_size(struct tg3 *tp)  in tg3_get_eeprom_size()  argument
14322 	tp->nvram_size = EEPROM_CHIP_SIZE;  in tg3_get_eeprom_size()
14324 	if (tg3_nvram_read(tp, 0, &magic) != 0)  in tg3_get_eeprom_size()
14339 	while (cursize < tp->nvram_size) {  in tg3_get_eeprom_size()
14340 		if (tg3_nvram_read(tp, cursize, &val) != 0)  in tg3_get_eeprom_size()
14349 	tp->nvram_size = cursize;  in tg3_get_eeprom_size()
14352 static void tg3_get_nvram_size(struct tg3 *tp)  in tg3_get_nvram_size()  argument
14356 	if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)  in tg3_get_nvram_size()
14361 		tg3_get_eeprom_size(tp);  in tg3_get_nvram_size()
14365 	if (tg3_nvram_read(tp, 0xf0, &val) == 0) {  in tg3_get_nvram_size()
14378 			tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;  in tg3_get_nvram_size()
14382 	tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_nvram_size()
14385 static void tg3_get_nvram_info(struct tg3 *tp)  in tg3_get_nvram_info()  argument
14391 		tg3_flag_set(tp, FLASH);  in tg3_get_nvram_info()
14397 	if (tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_get_nvram_info()
14398 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_get_nvram_info()
14401 			tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14402 			tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;  in tg3_get_nvram_info()
14403 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14406 			tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14407 			tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;  in tg3_get_nvram_info()
14410 			tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14411 			tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_nvram_info()
14412 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14415 			tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_nvram_info()
14416 			tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;  in tg3_get_nvram_info()
14417 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14420 			tp->nvram_jedecnum = JEDEC_SAIFUN;  in tg3_get_nvram_info()
14421 			tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;  in tg3_get_nvram_info()
14425 			tp->nvram_jedecnum = JEDEC_SST;  in tg3_get_nvram_info()
14426 			tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;  in tg3_get_nvram_info()
14430 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14431 		tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;  in tg3_get_nvram_info()
14432 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14436 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)  in tg3_nvram_get_pagesize()  argument
14440 		tp->nvram_pagesize = 256;  in tg3_nvram_get_pagesize()
14443 		tp->nvram_pagesize = 512;  in tg3_nvram_get_pagesize()
14446 		tp->nvram_pagesize = 1024;  in tg3_nvram_get_pagesize()
14449 		tp->nvram_pagesize = 2048;  in tg3_nvram_get_pagesize()
14452 		tp->nvram_pagesize = 4096;  in tg3_nvram_get_pagesize()
14455 		tp->nvram_pagesize = 264;  in tg3_nvram_get_pagesize()
14458 		tp->nvram_pagesize = 528;  in tg3_nvram_get_pagesize()
14463 static void tg3_get_5752_nvram_info(struct tg3 *tp)  in tg3_get_5752_nvram_info()  argument
14471 		tg3_flag_set(tp, PROTECTED_NVRAM);  in tg3_get_5752_nvram_info()
14476 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5752_nvram_info()
14477 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5752_nvram_info()
14480 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5752_nvram_info()
14481 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5752_nvram_info()
14482 		tg3_flag_set(tp, FLASH);  in tg3_get_5752_nvram_info()
14487 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5752_nvram_info()
14488 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5752_nvram_info()
14489 		tg3_flag_set(tp, FLASH);  in tg3_get_5752_nvram_info()
14493 	if (tg3_flag(tp, FLASH)) {  in tg3_get_5752_nvram_info()
14494 		tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5752_nvram_info()
14497 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5752_nvram_info()
14504 static void tg3_get_5755_nvram_info(struct tg3 *tp)  in tg3_get_5755_nvram_info()  argument
14512 		tg3_flag_set(tp, PROTECTED_NVRAM);  in tg3_get_5755_nvram_info()
14522 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5755_nvram_info()
14523 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5755_nvram_info()
14524 		tg3_flag_set(tp, FLASH);  in tg3_get_5755_nvram_info()
14525 		tp->nvram_pagesize = 264;  in tg3_get_5755_nvram_info()
14528 			tp->nvram_size = (protect ? 0x3e200 :  in tg3_get_5755_nvram_info()
14531 			tp->nvram_size = (protect ? 0x1f200 :  in tg3_get_5755_nvram_info()
14534 			tp->nvram_size = (protect ? 0x1f200 :  in tg3_get_5755_nvram_info()
14540 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5755_nvram_info()
14541 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5755_nvram_info()
14542 		tg3_flag_set(tp, FLASH);  in tg3_get_5755_nvram_info()
14543 		tp->nvram_pagesize = 256;  in tg3_get_5755_nvram_info()
14545 			tp->nvram_size = (protect ?  in tg3_get_5755_nvram_info()
14549 			tp->nvram_size = (protect ?  in tg3_get_5755_nvram_info()
14553 			tp->nvram_size = (protect ?  in tg3_get_5755_nvram_info()
14560 static void tg3_get_5787_nvram_info(struct tg3 *tp)  in tg3_get_5787_nvram_info()  argument
14571 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5787_nvram_info()
14572 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5787_nvram_info()
14573 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5787_nvram_info()
14582 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5787_nvram_info()
14583 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5787_nvram_info()
14584 		tg3_flag_set(tp, FLASH);  in tg3_get_5787_nvram_info()
14585 		tp->nvram_pagesize = 264;  in tg3_get_5787_nvram_info()
14590 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5787_nvram_info()
14591 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5787_nvram_info()
14592 		tg3_flag_set(tp, FLASH);  in tg3_get_5787_nvram_info()
14593 		tp->nvram_pagesize = 256;  in tg3_get_5787_nvram_info()
14598 static void tg3_get_5761_nvram_info(struct tg3 *tp)  in tg3_get_5761_nvram_info()  argument
14606 		tg3_flag_set(tp, PROTECTED_NVRAM);  in tg3_get_5761_nvram_info()
14620 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5761_nvram_info()
14621 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5761_nvram_info()
14622 		tg3_flag_set(tp, FLASH);  in tg3_get_5761_nvram_info()
14623 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5761_nvram_info()
14624 		tp->nvram_pagesize = 256;  in tg3_get_5761_nvram_info()
14634 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5761_nvram_info()
14635 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5761_nvram_info()
14636 		tg3_flag_set(tp, FLASH);  in tg3_get_5761_nvram_info()
14637 		tp->nvram_pagesize = 256;  in tg3_get_5761_nvram_info()
14642 		tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);  in tg3_get_5761_nvram_info()
14649 			tp->nvram_size = TG3_NVRAM_SIZE_2MB;  in tg3_get_5761_nvram_info()
14655 			tp->nvram_size = TG3_NVRAM_SIZE_1MB;  in tg3_get_5761_nvram_info()
14661 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_5761_nvram_info()
14667 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5761_nvram_info()
14673 static void tg3_get_5906_nvram_info(struct tg3 *tp)  in tg3_get_5906_nvram_info()  argument
14675 	tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5906_nvram_info()
14676 	tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5906_nvram_info()
14677 	tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5906_nvram_info()
14680 static void tg3_get_57780_nvram_info(struct tg3 *tp)  in tg3_get_57780_nvram_info()  argument
14689 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_57780_nvram_info()
14690 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_57780_nvram_info()
14691 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_57780_nvram_info()
14703 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_57780_nvram_info()
14704 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_57780_nvram_info()
14705 		tg3_flag_set(tp, FLASH);  in tg3_get_57780_nvram_info()
14711 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_57780_nvram_info()
14715 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_57780_nvram_info()
14719 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_57780_nvram_info()
14726 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_57780_nvram_info()
14727 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_57780_nvram_info()
14728 		tg3_flag_set(tp, FLASH);  in tg3_get_57780_nvram_info()
14732 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_57780_nvram_info()
14735 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_57780_nvram_info()
14738 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_57780_nvram_info()
14743 		tg3_flag_set(tp, NO_NVRAM);  in tg3_get_57780_nvram_info()
14747 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_57780_nvram_info()
14748 	if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)  in tg3_get_57780_nvram_info()
14749 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_57780_nvram_info()
14753 static void tg3_get_5717_nvram_info(struct tg3 *tp)  in tg3_get_5717_nvram_info()  argument
14762 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5717_nvram_info()
14763 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5717_nvram_info()
14764 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5717_nvram_info()
14776 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5717_nvram_info()
14777 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5717_nvram_info()
14778 		tg3_flag_set(tp, FLASH);  in tg3_get_5717_nvram_info()
14786 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5717_nvram_info()
14789 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5717_nvram_info()
14803 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5717_nvram_info()
14804 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5717_nvram_info()
14805 		tg3_flag_set(tp, FLASH);  in tg3_get_5717_nvram_info()
14814 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5717_nvram_info()
14817 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5717_nvram_info()
14822 		tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5717_nvram_info()
14826 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5717_nvram_info()
14827 	if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)  in tg3_get_5717_nvram_info()
14828 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5717_nvram_info()
14831 static void tg3_get_5720_nvram_info(struct tg3 *tp)  in tg3_get_5720_nvram_info()  argument
14838 	if (tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_get_5720_nvram_info()
14840 			tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5720_nvram_info()
14850 			tp->nvram_pagesize = 4096;  in tg3_get_5720_nvram_info()
14851 			tp->nvram_jedecnum = JEDEC_MACRONIX;  in tg3_get_5720_nvram_info()
14852 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14853 			tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5720_nvram_info()
14854 			tg3_flag_set(tp, FLASH);  in tg3_get_5720_nvram_info()
14856 			tp->nvram_size =  in tg3_get_5720_nvram_info()
14880 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5720_nvram_info()
14881 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14886 			tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5720_nvram_info()
14888 			tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;  in tg3_get_5720_nvram_info()
14902 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5720_nvram_info()
14903 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14904 		tg3_flag_set(tp, FLASH);  in tg3_get_5720_nvram_info()
14910 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5720_nvram_info()
14915 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_5720_nvram_info()
14919 			tp->nvram_size = TG3_NVRAM_SIZE_1MB;  in tg3_get_5720_nvram_info()
14922 			if (tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_get_5720_nvram_info()
14923 				tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5720_nvram_info()
14945 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5720_nvram_info()
14946 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14947 		tg3_flag_set(tp, FLASH);  in tg3_get_5720_nvram_info()
14954 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5720_nvram_info()
14960 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_5720_nvram_info()
14966 			tp->nvram_size = TG3_NVRAM_SIZE_1MB;  in tg3_get_5720_nvram_info()
14969 			if (tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_get_5720_nvram_info()
14970 				tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5720_nvram_info()
14975 		tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5720_nvram_info()
14979 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5720_nvram_info()
14980 	if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)  in tg3_get_5720_nvram_info()
14981 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5720_nvram_info()
14983 	if (tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_get_5720_nvram_info()
14986 		if (tg3_nvram_read(tp, 0, &val))  in tg3_get_5720_nvram_info()
14991 			tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5720_nvram_info()
14996 static void tg3_nvram_init(struct tg3 *tp)  in tg3_nvram_init()  argument
14998 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_nvram_init()
15000 		tg3_flag_clear(tp, NVRAM);  in tg3_nvram_init()
15001 		tg3_flag_clear(tp, NVRAM_BUFFERED);  in tg3_nvram_init()
15002 		tg3_flag_set(tp, NO_NVRAM);  in tg3_nvram_init()
15018 	if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_nvram_init()
15019 	    tg3_asic_rev(tp) != ASIC_REV_5701) {  in tg3_nvram_init()
15020 		tg3_flag_set(tp, NVRAM);  in tg3_nvram_init()
15022 		if (tg3_nvram_lock(tp)) {  in tg3_nvram_init()
15023 			netdev_warn(tp->dev,  in tg3_nvram_init()
15028 		tg3_enable_nvram_access(tp);  in tg3_nvram_init()
15030 		tp->nvram_size = 0;  in tg3_nvram_init()
15032 		if (tg3_asic_rev(tp) == ASIC_REV_5752)  in tg3_nvram_init()
15033 			tg3_get_5752_nvram_info(tp);  in tg3_nvram_init()
15034 		else if (tg3_asic_rev(tp) == ASIC_REV_5755)  in tg3_nvram_init()
15035 			tg3_get_5755_nvram_info(tp);  in tg3_nvram_init()
15036 		else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||  in tg3_nvram_init()
15037 			 tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_nvram_init()
15038 			 tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_nvram_init()
15039 			tg3_get_5787_nvram_info(tp);  in tg3_nvram_init()
15040 		else if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_nvram_init()
15041 			tg3_get_5761_nvram_info(tp);  in tg3_nvram_init()
15042 		else if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_nvram_init()
15043 			tg3_get_5906_nvram_info(tp);  in tg3_nvram_init()
15044 		else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_nvram_init()
15045 			 tg3_flag(tp, 57765_CLASS))  in tg3_nvram_init()
15046 			tg3_get_57780_nvram_info(tp);  in tg3_nvram_init()
15047 		else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_nvram_init()
15048 			 tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_nvram_init()
15049 			tg3_get_5717_nvram_info(tp);  in tg3_nvram_init()
15050 		else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_nvram_init()
15051 			 tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_nvram_init()
15052 			tg3_get_5720_nvram_info(tp);  in tg3_nvram_init()
15054 			tg3_get_nvram_info(tp);  in tg3_nvram_init()
15056 		if (tp->nvram_size == 0)  in tg3_nvram_init()
15057 			tg3_get_nvram_size(tp);  in tg3_nvram_init()
15059 		tg3_disable_nvram_access(tp);  in tg3_nvram_init()
15060 		tg3_nvram_unlock(tp);  in tg3_nvram_init()
15063 		tg3_flag_clear(tp, NVRAM);  in tg3_nvram_init()
15064 		tg3_flag_clear(tp, NVRAM_BUFFERED);  in tg3_nvram_init()
15066 		tg3_get_eeprom_size(tp);  in tg3_nvram_init()
15139 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)  in tg3_lookup_by_subsys()  argument
15145 		     tp->pdev->subsystem_vendor) &&  in tg3_lookup_by_subsys()
15147 		     tp->pdev->subsystem_device))  in tg3_lookup_by_subsys()
15153 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)  in tg3_get_eeprom_hw_cfg()  argument
15157 	tp->phy_id = TG3_PHY_ID_INVALID;  in tg3_get_eeprom_hw_cfg()
15158 	tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15161 	tg3_flag_set(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15162 	tg3_flag_set(tp, WOL_CAP);  in tg3_get_eeprom_hw_cfg()
15164 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_eeprom_hw_cfg()
15166 			tg3_flag_clear(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15167 			tg3_flag_set(tp, IS_NIC);  in tg3_get_eeprom_hw_cfg()
15171 			tg3_flag_set(tp, ASPM_WORKAROUND);  in tg3_get_eeprom_hw_cfg()
15174 			tg3_flag_set(tp, WOL_ENABLE);  in tg3_get_eeprom_hw_cfg()
15175 			device_set_wakeup_enable(&tp->pdev->dev, true);  in tg3_get_eeprom_hw_cfg()
15180 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);  in tg3_get_eeprom_hw_cfg()
15187 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);  in tg3_get_eeprom_hw_cfg()
15188 		tp->nic_sram_data_cfg = nic_cfg;  in tg3_get_eeprom_hw_cfg()
15190 		tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);  in tg3_get_eeprom_hw_cfg()
15192 		if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_get_eeprom_hw_cfg()
15193 		    tg3_asic_rev(tp) != ASIC_REV_5701 &&  in tg3_get_eeprom_hw_cfg()
15194 		    tg3_asic_rev(tp) != ASIC_REV_5703 &&  in tg3_get_eeprom_hw_cfg()
15196 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);  in tg3_get_eeprom_hw_cfg()
15198 		if (tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_get_eeprom_hw_cfg()
15199 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);  in tg3_get_eeprom_hw_cfg()
15201 		if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_eeprom_hw_cfg()
15202 		    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_eeprom_hw_cfg()
15203 		    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_get_eeprom_hw_cfg()
15204 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);  in tg3_get_eeprom_hw_cfg()
15210 		tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);  in tg3_get_eeprom_hw_cfg()
15221 		tp->phy_id = eeprom_phy_id;  in tg3_get_eeprom_hw_cfg()
15223 			if (!tg3_flag(tp, 5705_PLUS))  in tg3_get_eeprom_hw_cfg()
15224 				tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;  in tg3_get_eeprom_hw_cfg()
15226 				tp->phy_flags |= TG3_PHYFLG_MII_SERDES;  in tg3_get_eeprom_hw_cfg()
15229 		if (tg3_flag(tp, 5750_PLUS))  in tg3_get_eeprom_hw_cfg()
15238 			tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15242 			tp->led_ctrl = LED_CTRL_MODE_PHY_2;  in tg3_get_eeprom_hw_cfg()
15246 			tp->led_ctrl = LED_CTRL_MODE_MAC;  in tg3_get_eeprom_hw_cfg()
15251 			if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_eeprom_hw_cfg()
15252 			    tg3_asic_rev(tp) == ASIC_REV_5701)  in tg3_get_eeprom_hw_cfg()
15253 				tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15258 			tp->led_ctrl = LED_CTRL_MODE_SHARED;  in tg3_get_eeprom_hw_cfg()
15259 			if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&  in tg3_get_eeprom_hw_cfg()
15260 			    tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)  in tg3_get_eeprom_hw_cfg()
15261 				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |  in tg3_get_eeprom_hw_cfg()
15264 			if (tg3_flag(tp, 5717_PLUS) ||  in tg3_get_eeprom_hw_cfg()
15265 			    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_eeprom_hw_cfg()
15266 				tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |  in tg3_get_eeprom_hw_cfg()
15272 			tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;  in tg3_get_eeprom_hw_cfg()
15276 			tp->led_ctrl = LED_CTRL_MODE_COMBO;  in tg3_get_eeprom_hw_cfg()
15277 			if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)  in tg3_get_eeprom_hw_cfg()
15278 				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |  in tg3_get_eeprom_hw_cfg()
15284 		if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_eeprom_hw_cfg()
15285 		     tg3_asic_rev(tp) == ASIC_REV_5701) &&  in tg3_get_eeprom_hw_cfg()
15286 		    tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)  in tg3_get_eeprom_hw_cfg()
15287 			tp->led_ctrl = LED_CTRL_MODE_PHY_2;  in tg3_get_eeprom_hw_cfg()
15289 		if (tg3_chip_rev(tp) == CHIPREV_5784_AX)  in tg3_get_eeprom_hw_cfg()
15290 			tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15293 			tg3_flag_set(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15294 			if ((tp->pdev->subsystem_vendor ==  in tg3_get_eeprom_hw_cfg()
15296 			    (tp->pdev->subsystem_device == 0x205a ||  in tg3_get_eeprom_hw_cfg()
15297 			     tp->pdev->subsystem_device == 0x2063))  in tg3_get_eeprom_hw_cfg()
15298 				tg3_flag_clear(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15300 			tg3_flag_clear(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15301 			tg3_flag_set(tp, IS_NIC);  in tg3_get_eeprom_hw_cfg()
15305 			tg3_flag_set(tp, ENABLE_ASF);  in tg3_get_eeprom_hw_cfg()
15306 			if (tg3_flag(tp, 5750_PLUS))  in tg3_get_eeprom_hw_cfg()
15307 				tg3_flag_set(tp, ASF_NEW_HANDSHAKE);  in tg3_get_eeprom_hw_cfg()
15311 		    tg3_flag(tp, 5750_PLUS))  in tg3_get_eeprom_hw_cfg()
15312 			tg3_flag_set(tp, ENABLE_APE);  in tg3_get_eeprom_hw_cfg()
15314 		if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&  in tg3_get_eeprom_hw_cfg()
15316 			tg3_flag_clear(tp, WOL_CAP);  in tg3_get_eeprom_hw_cfg()
15318 		if (tg3_flag(tp, WOL_CAP) &&  in tg3_get_eeprom_hw_cfg()
15320 			tg3_flag_set(tp, WOL_ENABLE);  in tg3_get_eeprom_hw_cfg()
15321 			device_set_wakeup_enable(&tp->pdev->dev, true);  in tg3_get_eeprom_hw_cfg()
15325 			tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;  in tg3_get_eeprom_hw_cfg()
15330 			tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;  in tg3_get_eeprom_hw_cfg()
15332 		if ((tg3_flag(tp, 57765_PLUS) ||  in tg3_get_eeprom_hw_cfg()
15333 		     (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_get_eeprom_hw_cfg()
15334 		      tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&  in tg3_get_eeprom_hw_cfg()
15336 			tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;  in tg3_get_eeprom_hw_cfg()
15338 		if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_get_eeprom_hw_cfg()
15341 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);  in tg3_get_eeprom_hw_cfg()
15342 			if (tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_get_eeprom_hw_cfg()
15343 			    !tg3_flag(tp, 57765_PLUS) &&  in tg3_get_eeprom_hw_cfg()
15345 				tg3_flag_set(tp, ASPM_WORKAROUND);  in tg3_get_eeprom_hw_cfg()
15347 				tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;  in tg3_get_eeprom_hw_cfg()
15349 				tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;  in tg3_get_eeprom_hw_cfg()
15353 			tg3_flag_set(tp, RGMII_INBAND_DISABLE);  in tg3_get_eeprom_hw_cfg()
15355 			tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);  in tg3_get_eeprom_hw_cfg()
15357 			tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);  in tg3_get_eeprom_hw_cfg()
15360 			tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;  in tg3_get_eeprom_hw_cfg()
15363 	if (tg3_flag(tp, WOL_CAP))  in tg3_get_eeprom_hw_cfg()
15364 		device_set_wakeup_enable(&tp->pdev->dev,  in tg3_get_eeprom_hw_cfg()
15365 					 tg3_flag(tp, WOL_ENABLE));  in tg3_get_eeprom_hw_cfg()
15367 		device_set_wakeup_capable(&tp->pdev->dev, false);  in tg3_get_eeprom_hw_cfg()
15370 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)  in tg3_ape_otp_read()  argument
15375 	err = tg3_nvram_lock(tp);  in tg3_ape_otp_read()
15379 	tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);  in tg3_ape_otp_read()
15380 	tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |  in tg3_ape_otp_read()
15382 	tg3_ape_read32(tp, TG3_APE_OTP_CTRL);  in tg3_ape_otp_read()
15386 		val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);  in tg3_ape_otp_read()
15388 			*val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);  in tg3_ape_otp_read()
15394 	tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);  in tg3_ape_otp_read()
15396 	tg3_nvram_unlock(tp);  in tg3_ape_otp_read()
15403 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)  in tg3_issue_otp_command()  argument
15426 static u32 tg3_read_otp_phycfg(struct tg3 *tp)  in tg3_read_otp_phycfg()  argument
15432 	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))  in tg3_read_otp_phycfg()
15437 	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))  in tg3_read_otp_phycfg()
15444 	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))  in tg3_read_otp_phycfg()
15452 static void tg3_phy_init_link_config(struct tg3 *tp)  in tg3_phy_init_link_config()  argument
15456 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_init_link_config()
15457 		if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))  in tg3_phy_init_link_config()
15462 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_phy_init_link_config()
15471 	tp->link_config.advertising = adv;  in tg3_phy_init_link_config()
15472 	tp->link_config.speed = SPEED_UNKNOWN;  in tg3_phy_init_link_config()
15473 	tp->link_config.duplex = DUPLEX_UNKNOWN;  in tg3_phy_init_link_config()
15474 	tp->link_config.autoneg = AUTONEG_ENABLE;  in tg3_phy_init_link_config()
15475 	tp->link_config.active_speed = SPEED_UNKNOWN;  in tg3_phy_init_link_config()
15476 	tp->link_config.active_duplex = DUPLEX_UNKNOWN;  in tg3_phy_init_link_config()
15478 	tp->old_link = -1;  in tg3_phy_init_link_config()
15481 static int tg3_phy_probe(struct tg3 *tp)  in tg3_phy_probe()  argument
15488 	tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_phy_probe()
15489 	tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in tg3_phy_probe()
15491 	if (tg3_flag(tp, ENABLE_APE)) {  in tg3_phy_probe()
15492 		switch (tp->pci_fn) {  in tg3_phy_probe()
15494 			tp->phy_ape_lock = TG3_APE_LOCK_PHY0;  in tg3_phy_probe()
15497 			tp->phy_ape_lock = TG3_APE_LOCK_PHY1;  in tg3_phy_probe()
15500 			tp->phy_ape_lock = TG3_APE_LOCK_PHY2;  in tg3_phy_probe()
15503 			tp->phy_ape_lock = TG3_APE_LOCK_PHY3;  in tg3_phy_probe()
15508 	if (!tg3_flag(tp, ENABLE_ASF) &&  in tg3_phy_probe()
15509 	    !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&  in tg3_phy_probe()
15510 	    !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))  in tg3_phy_probe()
15511 		tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |  in tg3_phy_probe()
15514 	if (tg3_flag(tp, USE_PHYLIB))  in tg3_phy_probe()
15515 		return tg3_phy_init(tp);  in tg3_phy_probe()
15521 	if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {  in tg3_phy_probe()
15529 		err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);  in tg3_phy_probe()
15530 		err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);  in tg3_phy_probe()
15540 		tp->phy_id = hw_phy_id;  in tg3_phy_probe()
15542 			tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;  in tg3_phy_probe()
15544 			tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;  in tg3_phy_probe()
15546 		if (tp->phy_id != TG3_PHY_ID_INVALID) {  in tg3_phy_probe()
15556 			p = tg3_lookup_by_subsys(tp);  in tg3_phy_probe()
15558 				tp->phy_id = p->phy_id;  in tg3_phy_probe()
15559 			} else if (!tg3_flag(tp, IS_SSB_CORE)) {  in tg3_phy_probe()
15570 			if (!tp->phy_id ||  in tg3_phy_probe()
15571 			    tp->phy_id == TG3_PHY_ID_BCM8002)  in tg3_phy_probe()
15572 				tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;  in tg3_phy_probe()
15576 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&  in tg3_phy_probe()
15577 	    (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_phy_probe()
15578 	     tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_phy_probe()
15579 	     tg3_asic_rev(tp) == ASIC_REV_57766 ||  in tg3_phy_probe()
15580 	     tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_phy_probe()
15581 	     (tg3_asic_rev(tp) == ASIC_REV_5717 &&  in tg3_phy_probe()
15582 	      tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||  in tg3_phy_probe()
15583 	     (tg3_asic_rev(tp) == ASIC_REV_57765 &&  in tg3_phy_probe()
15584 	      tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {  in tg3_phy_probe()
15585 		tp->phy_flags |= TG3_PHYFLG_EEE_CAP;  in tg3_phy_probe()
15587 		tp->eee.supported = SUPPORTED_100baseT_Full |  in tg3_phy_probe()
15589 		tp->eee.advertised = ADVERTISED_100baseT_Full |  in tg3_phy_probe()
15591 		tp->eee.eee_enabled = 1;  in tg3_phy_probe()
15592 		tp->eee.tx_lpi_enabled = 1;  in tg3_phy_probe()
15593 		tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;  in tg3_phy_probe()
15596 	tg3_phy_init_link_config(tp);  in tg3_phy_probe()
15598 	if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&  in tg3_phy_probe()
15599 	    !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&  in tg3_phy_probe()
15600 	    !tg3_flag(tp, ENABLE_APE) &&  in tg3_phy_probe()
15601 	    !tg3_flag(tp, ENABLE_ASF)) {  in tg3_phy_probe()
15604 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_phy_probe()
15605 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_phy_probe()
15609 		err = tg3_phy_reset(tp);  in tg3_phy_probe()
15613 		tg3_phy_set_wirespeed(tp);  in tg3_phy_probe()
15615 		if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {  in tg3_phy_probe()
15616 			tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,  in tg3_phy_probe()
15617 					    tp->link_config.flowctrl);  in tg3_phy_probe()
15619 			tg3_writephy(tp, MII_BMCR,  in tg3_phy_probe()
15625 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_phy_probe()
15626 		err = tg3_init_5401phy_dsp(tp);  in tg3_phy_probe()
15630 		err = tg3_init_5401phy_dsp(tp);  in tg3_phy_probe()
15636 static void tg3_read_vpd(struct tg3 *tp)  in tg3_read_vpd()  argument
15643 	vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);  in tg3_read_vpd()
15679 		if (len >= sizeof(tp->fw_ver))  in tg3_read_vpd()
15680 			len = sizeof(tp->fw_ver) - 1;  in tg3_read_vpd()
15681 		memset(tp->fw_ver, 0, sizeof(tp->fw_ver));  in tg3_read_vpd()
15682 		snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,  in tg3_read_vpd()
15699 	memcpy(tp->board_part_number, &vpd_data[i], len);  in tg3_read_vpd()
15703 	if (tp->board_part_number[0])  in tg3_read_vpd()
15707 	if (tg3_asic_rev(tp) == ASIC_REV_5717) {  in tg3_read_vpd()
15708 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||  in tg3_read_vpd()
15709 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)  in tg3_read_vpd()
15710 			strcpy(tp->board_part_number, "BCM5717");  in tg3_read_vpd()
15711 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)  in tg3_read_vpd()
15712 			strcpy(tp->board_part_number, "BCM5718");  in tg3_read_vpd()
15715 	} else if (tg3_asic_rev(tp) == ASIC_REV_57780) {  in tg3_read_vpd()
15716 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)  in tg3_read_vpd()
15717 			strcpy(tp->board_part_number, "BCM57780");  in tg3_read_vpd()
15718 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)  in tg3_read_vpd()
15719 			strcpy(tp->board_part_number, "BCM57760");  in tg3_read_vpd()
15720 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)  in tg3_read_vpd()
15721 			strcpy(tp->board_part_number, "BCM57790");  in tg3_read_vpd()
15722 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)  in tg3_read_vpd()
15723 			strcpy(tp->board_part_number, "BCM57788");  in tg3_read_vpd()
15726 	} else if (tg3_asic_rev(tp) == ASIC_REV_57765) {  in tg3_read_vpd()
15727 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)  in tg3_read_vpd()
15728 			strcpy(tp->board_part_number, "BCM57761");  in tg3_read_vpd()
15729 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)  in tg3_read_vpd()
15730 			strcpy(tp->board_part_number, "BCM57765");  in tg3_read_vpd()
15731 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)  in tg3_read_vpd()
15732 			strcpy(tp->board_part_number, "BCM57781");  in tg3_read_vpd()
15733 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)  in tg3_read_vpd()
15734 			strcpy(tp->board_part_number, "BCM57785");  in tg3_read_vpd()
15735 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)  in tg3_read_vpd()
15736 			strcpy(tp->board_part_number, "BCM57791");  in tg3_read_vpd()
15737 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)  in tg3_read_vpd()
15738 			strcpy(tp->board_part_number, "BCM57795");  in tg3_read_vpd()
15741 	} else if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_read_vpd()
15742 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)  in tg3_read_vpd()
15743 			strcpy(tp->board_part_number, "BCM57762");  in tg3_read_vpd()
15744 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)  in tg3_read_vpd()
15745 			strcpy(tp->board_part_number, "BCM57766");  in tg3_read_vpd()
15746 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)  in tg3_read_vpd()
15747 			strcpy(tp->board_part_number, "BCM57782");  in tg3_read_vpd()
15748 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)  in tg3_read_vpd()
15749 			strcpy(tp->board_part_number, "BCM57786");  in tg3_read_vpd()
15752 	} else if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_read_vpd()
15753 		strcpy(tp->board_part_number, "BCM95906");  in tg3_read_vpd()
15756 		strcpy(tp->board_part_number, "none");  in tg3_read_vpd()
15760 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)  in tg3_fw_img_is_valid()  argument
15764 	if (tg3_nvram_read(tp, offset, &val) ||  in tg3_fw_img_is_valid()
15766 	    tg3_nvram_read(tp, offset + 4, &val) ||  in tg3_fw_img_is_valid()
15773 static void tg3_read_bc_ver(struct tg3 *tp)  in tg3_read_bc_ver()  argument
15779 	if (tg3_nvram_read(tp, 0xc, &offset) ||  in tg3_read_bc_ver()
15780 	    tg3_nvram_read(tp, 0x4, &start))  in tg3_read_bc_ver()
15783 	offset = tg3_nvram_logical_addr(tp, offset);  in tg3_read_bc_ver()
15785 	if (tg3_nvram_read(tp, offset, &val))  in tg3_read_bc_ver()
15789 		if (tg3_nvram_read(tp, offset + 4, &val))  in tg3_read_bc_ver()
15796 	dst_off = strlen(tp->fw_ver);  in tg3_read_bc_ver()
15800 		    tg3_nvram_read(tp, offset + 8, &ver_offset))  in tg3_read_bc_ver()
15806 			if (tg3_nvram_read_be32(tp, offset + i, &v))  in tg3_read_bc_ver()
15809 			memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));  in tg3_read_bc_ver()
15814 		if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))  in tg3_read_bc_ver()
15820 		snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,  in tg3_read_bc_ver()
15825 static void tg3_read_hwsb_ver(struct tg3 *tp)  in tg3_read_hwsb_ver()  argument
15830 	if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))  in tg3_read_hwsb_ver()
15838 	snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);  in tg3_read_hwsb_ver()
15841 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)  in tg3_read_sb_ver()  argument
15845 	strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);  in tg3_read_sb_ver()
15873 	if (tg3_nvram_read(tp, offset, &val))  in tg3_read_sb_ver()
15885 	offset = strlen(tp->fw_ver);  in tg3_read_sb_ver()
15886 	snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,  in tg3_read_sb_ver()
15890 		offset = strlen(tp->fw_ver);  in tg3_read_sb_ver()
15892 			tp->fw_ver[offset] = 'a' + build - 1;  in tg3_read_sb_ver()
15896 static void tg3_read_mgmtfw_ver(struct tg3 *tp)  in tg3_read_mgmtfw_ver()  argument
15904 		if (tg3_nvram_read(tp, offset, &val))  in tg3_read_mgmtfw_ver()
15914 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_read_mgmtfw_ver()
15916 	else if (tg3_nvram_read(tp, offset - 4, &start))  in tg3_read_mgmtfw_ver()
15919 	if (tg3_nvram_read(tp, offset + 4, &offset) ||  in tg3_read_mgmtfw_ver()
15920 	    !tg3_fw_img_is_valid(tp, offset) ||  in tg3_read_mgmtfw_ver()
15921 	    tg3_nvram_read(tp, offset + 8, &val))  in tg3_read_mgmtfw_ver()
15926 	vlen = strlen(tp->fw_ver);  in tg3_read_mgmtfw_ver()
15928 	tp->fw_ver[vlen++] = ',';  in tg3_read_mgmtfw_ver()
15929 	tp->fw_ver[vlen++] = ' ';  in tg3_read_mgmtfw_ver()
15933 		if (tg3_nvram_read_be32(tp, offset, &v))  in tg3_read_mgmtfw_ver()
15939 			memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);  in tg3_read_mgmtfw_ver()
15943 		memcpy(&tp->fw_ver[vlen], &v, sizeof(v));  in tg3_read_mgmtfw_ver()
15948 static void tg3_probe_ncsi(struct tg3 *tp)  in tg3_probe_ncsi()  argument
15952 	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);  in tg3_probe_ncsi()
15956 	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_probe_ncsi()
15960 	if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)  in tg3_probe_ncsi()
15961 		tg3_flag_set(tp, APE_HAS_NCSI);  in tg3_probe_ncsi()
15964 static void tg3_read_dash_ver(struct tg3 *tp)  in tg3_read_dash_ver()  argument
15970 	apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);  in tg3_read_dash_ver()
15972 	if (tg3_flag(tp, APE_HAS_NCSI))  in tg3_read_dash_ver()
15974 	else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)  in tg3_read_dash_ver()
15979 	vlen = strlen(tp->fw_ver);  in tg3_read_dash_ver()
15981 	snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",  in tg3_read_dash_ver()
15989 static void tg3_read_otp_ver(struct tg3 *tp)  in tg3_read_otp_ver()  argument
15993 	if (tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_read_otp_ver()
15996 	if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&  in tg3_read_otp_ver()
15997 	    !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&  in tg3_read_otp_ver()
16009 		vlen = strlen(tp->fw_ver);  in tg3_read_otp_ver()
16010 		snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);  in tg3_read_otp_ver()
16014 static void tg3_read_fw_ver(struct tg3 *tp)  in tg3_read_fw_ver()  argument
16019 	if (tp->fw_ver[0] != 0)  in tg3_read_fw_ver()
16022 	if (tg3_flag(tp, NO_NVRAM)) {  in tg3_read_fw_ver()
16023 		strcat(tp->fw_ver, "sb");  in tg3_read_fw_ver()
16024 		tg3_read_otp_ver(tp);  in tg3_read_fw_ver()
16028 	if (tg3_nvram_read(tp, 0, &val))  in tg3_read_fw_ver()
16032 		tg3_read_bc_ver(tp);  in tg3_read_fw_ver()
16034 		tg3_read_sb_ver(tp, val);  in tg3_read_fw_ver()
16036 		tg3_read_hwsb_ver(tp);  in tg3_read_fw_ver()
16038 	if (tg3_flag(tp, ENABLE_ASF)) {  in tg3_read_fw_ver()
16039 		if (tg3_flag(tp, ENABLE_APE)) {  in tg3_read_fw_ver()
16040 			tg3_probe_ncsi(tp);  in tg3_read_fw_ver()
16042 				tg3_read_dash_ver(tp);  in tg3_read_fw_ver()
16044 			tg3_read_mgmtfw_ver(tp);  in tg3_read_fw_ver()
16048 	tp->fw_ver[TG3_VER_SIZE - 1] = 0;  in tg3_read_fw_ver()
16051 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)  in tg3_rx_ret_ring_size()  argument
16053 	if (tg3_flag(tp, LRG_PROD_RING_CAP))  in tg3_rx_ret_ring_size()
16055 	else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))  in tg3_rx_ret_ring_size()
16068 static struct pci_dev *tg3_find_peer(struct tg3 *tp)  in tg3_find_peer()  argument
16071 	unsigned int func, devnr = tp->pdev->devfn & ~7;  in tg3_find_peer()
16074 		peer = pci_get_slot(tp->pdev->bus, devnr | func);  in tg3_find_peer()
16075 		if (peer && peer != tp->pdev)  in tg3_find_peer()
16083 		peer = tp->pdev;  in tg3_find_peer()
16096 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)  in tg3_detect_asic_rev()  argument
16098 	tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;  in tg3_detect_asic_rev()
16099 	if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {  in tg3_detect_asic_rev()
16105 		tg3_flag_set(tp, CPMU_PRESENT);  in tg3_detect_asic_rev()
16107 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||  in tg3_detect_asic_rev()
16108 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||  in tg3_detect_asic_rev()
16109 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||  in tg3_detect_asic_rev()
16110 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||  in tg3_detect_asic_rev()
16111 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||  in tg3_detect_asic_rev()
16112 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||  in tg3_detect_asic_rev()
16113 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||  in tg3_detect_asic_rev()
16114 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||  in tg3_detect_asic_rev()
16115 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||  in tg3_detect_asic_rev()
16116 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||  in tg3_detect_asic_rev()
16117 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)  in tg3_detect_asic_rev()
16119 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||  in tg3_detect_asic_rev()
16120 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||  in tg3_detect_asic_rev()
16121 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||  in tg3_detect_asic_rev()
16122 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||  in tg3_detect_asic_rev()
16123 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||  in tg3_detect_asic_rev()
16124 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||  in tg3_detect_asic_rev()
16125 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||  in tg3_detect_asic_rev()
16126 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||  in tg3_detect_asic_rev()
16127 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||  in tg3_detect_asic_rev()
16128 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)  in tg3_detect_asic_rev()
16133 		pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);  in tg3_detect_asic_rev()
16139 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)  in tg3_detect_asic_rev()
16140 		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;  in tg3_detect_asic_rev()
16142 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)  in tg3_detect_asic_rev()
16143 		tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;  in tg3_detect_asic_rev()
16145 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_detect_asic_rev()
16146 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_detect_asic_rev()
16147 	    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_detect_asic_rev()
16148 		tg3_flag_set(tp, 5717_PLUS);  in tg3_detect_asic_rev()
16150 	if (tg3_asic_rev(tp) == ASIC_REV_57765 ||  in tg3_detect_asic_rev()
16151 	    tg3_asic_rev(tp) == ASIC_REV_57766)  in tg3_detect_asic_rev()
16152 		tg3_flag_set(tp, 57765_CLASS);  in tg3_detect_asic_rev()
16154 	if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||  in tg3_detect_asic_rev()
16155 	     tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_detect_asic_rev()
16156 		tg3_flag_set(tp, 57765_PLUS);  in tg3_detect_asic_rev()
16159 	if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_detect_asic_rev()
16160 	    tg3_asic_rev(tp) == ASIC_REV_5787 ||  in tg3_detect_asic_rev()
16161 	    tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_detect_asic_rev()
16162 	    tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_detect_asic_rev()
16163 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_detect_asic_rev()
16164 	    tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_detect_asic_rev()
16165 	    tg3_flag(tp, 57765_PLUS))  in tg3_detect_asic_rev()
16166 		tg3_flag_set(tp, 5755_PLUS);  in tg3_detect_asic_rev()
16168 	if (tg3_asic_rev(tp) == ASIC_REV_5780 ||  in tg3_detect_asic_rev()
16169 	    tg3_asic_rev(tp) == ASIC_REV_5714)  in tg3_detect_asic_rev()
16170 		tg3_flag_set(tp, 5780_CLASS);  in tg3_detect_asic_rev()
16172 	if (tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_detect_asic_rev()
16173 	    tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_detect_asic_rev()
16174 	    tg3_asic_rev(tp) == ASIC_REV_5906 ||  in tg3_detect_asic_rev()
16175 	    tg3_flag(tp, 5755_PLUS) ||  in tg3_detect_asic_rev()
16176 	    tg3_flag(tp, 5780_CLASS))  in tg3_detect_asic_rev()
16177 		tg3_flag_set(tp, 5750_PLUS);  in tg3_detect_asic_rev()
16179 	if (tg3_asic_rev(tp) == ASIC_REV_5705 ||  in tg3_detect_asic_rev()
16180 	    tg3_flag(tp, 5750_PLUS))  in tg3_detect_asic_rev()
16181 		tg3_flag_set(tp, 5705_PLUS);  in tg3_detect_asic_rev()
16184 static bool tg3_10_100_only_device(struct tg3 *tp,  in tg3_10_100_only_device()  argument
16189 	if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&  in tg3_10_100_only_device()
16191 	    (tp->phy_flags & TG3_PHYFLG_IS_FET))  in tg3_10_100_only_device()
16195 		if (tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_10_100_only_device()
16206 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)  in tg3_get_invariants()  argument
16221 	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
16223 	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
16230 	pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
16232 	tp->misc_host_ctrl |= (misc_ctrl_reg &  in tg3_get_invariants()
16234 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
16235 			       tp->misc_host_ctrl);  in tg3_get_invariants()
16237 	tg3_detect_asic_rev(tp, misc_ctrl_reg);  in tg3_get_invariants()
16256 	if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||  in tg3_get_invariants()
16257 	    (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {  in tg3_get_invariants()
16289 			     tp->pdev->bus->number)) {  in tg3_get_invariants()
16290 				tg3_flag_set(tp, ICH_WORKAROUND);  in tg3_get_invariants()
16297 	if (tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_get_invariants()
16319 			     tp->pdev->bus->number) &&  in tg3_get_invariants()
16321 			     tp->pdev->bus->number)) {  in tg3_get_invariants()
16322 				tg3_flag_set(tp, 5701_DMA_BUG);  in tg3_get_invariants()
16335 	if (tg3_flag(tp, 5780_CLASS)) {  in tg3_get_invariants()
16336 		tg3_flag_set(tp, 40BIT_DMA_BUG);  in tg3_get_invariants()
16337 		tp->msi_cap = tp->pdev->msi_cap;  in tg3_get_invariants()
16347 			     tp->pdev->bus->number) &&  in tg3_get_invariants()
16349 			     tp->pdev->bus->number)) {  in tg3_get_invariants()
16350 				tg3_flag_set(tp, 40BIT_DMA_BUG);  in tg3_get_invariants()
16357 	if (tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_get_invariants()
16358 	    tg3_asic_rev(tp) == ASIC_REV_5714)  in tg3_get_invariants()
16359 		tp->pdev_peer = tg3_find_peer(tp);  in tg3_get_invariants()
16362 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)  in tg3_get_invariants()
16364 	else if (tg3_flag(tp, 57765_PLUS))  in tg3_get_invariants()
16365 		tg3_flag_set(tp, HW_TSO_3);  in tg3_get_invariants()
16366 	else if (tg3_flag(tp, 5755_PLUS) ||  in tg3_get_invariants()
16367 		 tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_invariants()
16368 		tg3_flag_set(tp, HW_TSO_2);  in tg3_get_invariants()
16369 	else if (tg3_flag(tp, 5750_PLUS)) {  in tg3_get_invariants()
16370 		tg3_flag_set(tp, HW_TSO_1);  in tg3_get_invariants()
16371 		tg3_flag_set(tp, TSO_BUG);  in tg3_get_invariants()
16372 		if (tg3_asic_rev(tp) == ASIC_REV_5750 &&  in tg3_get_invariants()
16373 		    tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)  in tg3_get_invariants()
16374 			tg3_flag_clear(tp, TSO_BUG);  in tg3_get_invariants()
16375 	} else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_get_invariants()
16376 		   tg3_asic_rev(tp) != ASIC_REV_5701 &&  in tg3_get_invariants()
16377 		   tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {  in tg3_get_invariants()
16378 		tg3_flag_set(tp, FW_TSO);  in tg3_get_invariants()
16379 		tg3_flag_set(tp, TSO_BUG);  in tg3_get_invariants()
16380 		if (tg3_asic_rev(tp) == ASIC_REV_5705)  in tg3_get_invariants()
16381 			tp->fw_needed = FIRMWARE_TG3TSO5;  in tg3_get_invariants()
16383 			tp->fw_needed = FIRMWARE_TG3TSO;  in tg3_get_invariants()
16387 	if (tg3_flag(tp, HW_TSO_1) ||  in tg3_get_invariants()
16388 	    tg3_flag(tp, HW_TSO_2) ||  in tg3_get_invariants()
16389 	    tg3_flag(tp, HW_TSO_3) ||  in tg3_get_invariants()
16390 	    tg3_flag(tp, FW_TSO)) {  in tg3_get_invariants()
16395 		tg3_flag_set(tp, TSO_CAPABLE);  in tg3_get_invariants()
16397 		tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_get_invariants()
16398 		tg3_flag_clear(tp, TSO_BUG);  in tg3_get_invariants()
16399 		tp->fw_needed = NULL;  in tg3_get_invariants()
16402 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)  in tg3_get_invariants()
16403 		tp->fw_needed = FIRMWARE_TG3;  in tg3_get_invariants()
16405 	if (tg3_asic_rev(tp) == ASIC_REV_57766)  in tg3_get_invariants()
16406 		tp->fw_needed = FIRMWARE_TG357766;  in tg3_get_invariants()
16408 	tp->irq_max = 1;  in tg3_get_invariants()
16410 	if (tg3_flag(tp, 5750_PLUS)) {  in tg3_get_invariants()
16411 		tg3_flag_set(tp, SUPPORT_MSI);  in tg3_get_invariants()
16412 		if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||  in tg3_get_invariants()
16413 		    tg3_chip_rev(tp) == CHIPREV_5750_BX ||  in tg3_get_invariants()
16414 		    (tg3_asic_rev(tp) == ASIC_REV_5714 &&  in tg3_get_invariants()
16415 		     tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&  in tg3_get_invariants()
16416 		     tp->pdev_peer == tp->pdev))  in tg3_get_invariants()
16417 			tg3_flag_clear(tp, SUPPORT_MSI);  in tg3_get_invariants()
16419 		if (tg3_flag(tp, 5755_PLUS) ||  in tg3_get_invariants()
16420 		    tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_invariants()
16421 			tg3_flag_set(tp, 1SHOT_MSI);  in tg3_get_invariants()
16424 		if (tg3_flag(tp, 57765_PLUS)) {  in tg3_get_invariants()
16425 			tg3_flag_set(tp, SUPPORT_MSIX);  in tg3_get_invariants()
16426 			tp->irq_max = TG3_IRQ_MAX_VECS;  in tg3_get_invariants()
16430 	tp->txq_max = 1;  in tg3_get_invariants()
16431 	tp->rxq_max = 1;  in tg3_get_invariants()
16432 	if (tp->irq_max > 1) {  in tg3_get_invariants()
16433 		tp->rxq_max = TG3_RSS_MAX_NUM_QS;  in tg3_get_invariants()
16434 		tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);  in tg3_get_invariants()
16436 		if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_invariants()
16437 		    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_get_invariants()
16438 			tp->txq_max = tp->irq_max - 1;  in tg3_get_invariants()
16441 	if (tg3_flag(tp, 5755_PLUS) ||  in tg3_get_invariants()
16442 	    tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_invariants()
16443 		tg3_flag_set(tp, SHORT_DMA_BUG);  in tg3_get_invariants()
16445 	if (tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_get_invariants()
16446 		tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;  in tg3_get_invariants()
16448 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_invariants()
16449 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_invariants()
16450 	    tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_get_invariants()
16451 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_invariants()
16452 		tg3_flag_set(tp, LRG_PROD_RING_CAP);  in tg3_get_invariants()
16454 	if (tg3_flag(tp, 57765_PLUS) &&  in tg3_get_invariants()
16455 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)  in tg3_get_invariants()
16456 		tg3_flag_set(tp, USE_JUMBO_BDFLAG);  in tg3_get_invariants()
16458 	if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_get_invariants()
16459 	    tg3_flag(tp, 5780_CLASS) ||  in tg3_get_invariants()
16460 	    tg3_flag(tp, USE_JUMBO_BDFLAG))  in tg3_get_invariants()
16461 		tg3_flag_set(tp, JUMBO_CAPABLE);  in tg3_get_invariants()
16463 	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,  in tg3_get_invariants()
16466 	if (pci_is_pcie(tp->pdev)) {  in tg3_get_invariants()
16469 		tg3_flag_set(tp, PCI_EXPRESS);  in tg3_get_invariants()
16471 		pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);  in tg3_get_invariants()
16473 			if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_invariants()
16474 				tg3_flag_clear(tp, HW_TSO_2);  in tg3_get_invariants()
16475 				tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_get_invariants()
16477 			if (tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_get_invariants()
16478 			    tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_get_invariants()
16479 			    tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||  in tg3_get_invariants()
16480 			    tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)  in tg3_get_invariants()
16481 				tg3_flag_set(tp, CLKREQ_BUG);  in tg3_get_invariants()
16482 		} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {  in tg3_get_invariants()
16483 			tg3_flag_set(tp, L1PLLPD_EN);  in tg3_get_invariants()
16485 	} else if (tg3_asic_rev(tp) == ASIC_REV_5785) {  in tg3_get_invariants()
16490 		tg3_flag_set(tp, PCI_EXPRESS);  in tg3_get_invariants()
16491 	} else if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_get_invariants()
16492 		   tg3_flag(tp, 5780_CLASS)) {  in tg3_get_invariants()
16493 		tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);  in tg3_get_invariants()
16494 		if (!tp->pcix_cap) {  in tg3_get_invariants()
16495 			dev_err(&tp->pdev->dev,  in tg3_get_invariants()
16501 			tg3_flag_set(tp, PCIX_MODE);  in tg3_get_invariants()
16511 	    !tg3_flag(tp, PCI_EXPRESS))  in tg3_get_invariants()
16512 		tg3_flag_set(tp, MBOX_WRITE_REORDER);  in tg3_get_invariants()
16514 	pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,  in tg3_get_invariants()
16515 			     &tp->pci_cacheline_sz);  in tg3_get_invariants()
16516 	pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,  in tg3_get_invariants()
16517 			     &tp->pci_lat_timer);  in tg3_get_invariants()
16518 	if (tg3_asic_rev(tp) == ASIC_REV_5703 &&  in tg3_get_invariants()
16519 	    tp->pci_lat_timer < 64) {  in tg3_get_invariants()
16520 		tp->pci_lat_timer = 64;  in tg3_get_invariants()
16521 		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,  in tg3_get_invariants()
16522 				      tp->pci_lat_timer);  in tg3_get_invariants()
16528 	if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {  in tg3_get_invariants()
16532 		tg3_flag_set(tp, TXD_MBOX_HWBUG);  in tg3_get_invariants()
16539 		if (tg3_flag(tp, PCIX_MODE)) {  in tg3_get_invariants()
16542 			tg3_flag_set(tp, PCIX_TARGET_HWBUG);  in tg3_get_invariants()
16548 			pci_read_config_dword(tp->pdev,  in tg3_get_invariants()
16549 					      tp->pdev->pm_cap + PCI_PM_CTRL,  in tg3_get_invariants()
16553 			pci_write_config_dword(tp->pdev,  in tg3_get_invariants()
16554 					       tp->pdev->pm_cap + PCI_PM_CTRL,  in tg3_get_invariants()
16558 			pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
16560 			pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
16565 		tg3_flag_set(tp, PCI_HIGH_SPEED);  in tg3_get_invariants()
16567 		tg3_flag_set(tp, PCI_32BIT);  in tg3_get_invariants()
16570 	if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&  in tg3_get_invariants()
16573 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);  in tg3_get_invariants()
16577 	tp->read32 = tg3_read32;  in tg3_get_invariants()
16578 	tp->write32 = tg3_write32;  in tg3_get_invariants()
16579 	tp->read32_mbox = tg3_read32;  in tg3_get_invariants()
16580 	tp->write32_mbox = tg3_write32;  in tg3_get_invariants()
16581 	tp->write32_tx_mbox = tg3_write32;  in tg3_get_invariants()
16582 	tp->write32_rx_mbox = tg3_write32;  in tg3_get_invariants()
16585 	if (tg3_flag(tp, PCIX_TARGET_HWBUG))  in tg3_get_invariants()
16586 		tp->write32 = tg3_write_indirect_reg32;  in tg3_get_invariants()
16587 	else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||  in tg3_get_invariants()
16588 		 (tg3_flag(tp, PCI_EXPRESS) &&  in tg3_get_invariants()
16589 		  tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {  in tg3_get_invariants()
16597 		tp->write32 = tg3_write_flush_reg32;  in tg3_get_invariants()
16600 	if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {  in tg3_get_invariants()
16601 		tp->write32_tx_mbox = tg3_write32_tx_mbox;  in tg3_get_invariants()
16602 		if (tg3_flag(tp, MBOX_WRITE_REORDER))  in tg3_get_invariants()
16603 			tp->write32_rx_mbox = tg3_write_flush_reg32;  in tg3_get_invariants()
16606 	if (tg3_flag(tp, ICH_WORKAROUND)) {  in tg3_get_invariants()
16607 		tp->read32 = tg3_read_indirect_reg32;  in tg3_get_invariants()
16608 		tp->write32 = tg3_write_indirect_reg32;  in tg3_get_invariants()
16609 		tp->read32_mbox = tg3_read_indirect_mbox;  in tg3_get_invariants()
16610 		tp->write32_mbox = tg3_write_indirect_mbox;  in tg3_get_invariants()
16611 		tp->write32_tx_mbox = tg3_write_indirect_mbox;  in tg3_get_invariants()
16612 		tp->write32_rx_mbox = tg3_write_indirect_mbox;  in tg3_get_invariants()
16614 		iounmap(tp->regs);  in tg3_get_invariants()
16615 		tp->regs = NULL;  in tg3_get_invariants()
16617 		pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
16619 		pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
16621 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_invariants()
16622 		tp->read32_mbox = tg3_read32_mbox_5906;  in tg3_get_invariants()
16623 		tp->write32_mbox = tg3_write32_mbox_5906;  in tg3_get_invariants()
16624 		tp->write32_tx_mbox = tg3_write32_mbox_5906;  in tg3_get_invariants()
16625 		tp->write32_rx_mbox = tg3_write32_mbox_5906;  in tg3_get_invariants()
16628 	if (tp->write32 == tg3_write_indirect_reg32 ||  in tg3_get_invariants()
16629 	    (tg3_flag(tp, PCIX_MODE) &&  in tg3_get_invariants()
16630 	     (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16631 	      tg3_asic_rev(tp) == ASIC_REV_5701)))  in tg3_get_invariants()
16632 		tg3_flag_set(tp, SRAM_USE_CONFIG);  in tg3_get_invariants()
16642 	tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;  in tg3_get_invariants()
16643 	if (tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_get_invariants()
16644 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_get_invariants()
16645 		if (tg3_flag(tp, PCIX_MODE)) {  in tg3_get_invariants()
16646 			pci_read_config_dword(tp->pdev,  in tg3_get_invariants()
16647 					      tp->pcix_cap + PCI_X_STATUS,  in tg3_get_invariants()
16649 			tp->pci_fn = val & 0x7;  in tg3_get_invariants()
16651 	} else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_invariants()
16652 		   tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_invariants()
16653 		   tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_get_invariants()
16654 		tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);  in tg3_get_invariants()
16658 		if (tg3_asic_rev(tp) == ASIC_REV_5717)  in tg3_get_invariants()
16659 			tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;  in tg3_get_invariants()
16661 			tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>  in tg3_get_invariants()
16665 	if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {  in tg3_get_invariants()
16666 		tp->write32_tx_mbox = tg3_write_flush_reg32;  in tg3_get_invariants()
16667 		tp->write32_rx_mbox = tg3_write_flush_reg32;  in tg3_get_invariants()
16678 	tg3_get_eeprom_hw_cfg(tp);  in tg3_get_invariants()
16680 	if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {  in tg3_get_invariants()
16681 		tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_get_invariants()
16682 		tg3_flag_clear(tp, TSO_BUG);  in tg3_get_invariants()
16683 		tp->fw_needed = NULL;  in tg3_get_invariants()
16686 	if (tg3_flag(tp, ENABLE_APE)) {  in tg3_get_invariants()
16693 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,  in tg3_get_invariants()
16696 		tg3_ape_lock_init(tp);  in tg3_get_invariants()
16697 		tp->ape_hb_interval =  in tg3_get_invariants()
16706 	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;  in tg3_get_invariants()
16707 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16708 	    tg3_flag(tp, EEPROM_WRITE_PROT))  in tg3_get_invariants()
16709 		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |  in tg3_get_invariants()
16714 	else if (tg3_asic_rev(tp) == ASIC_REV_5752)  in tg3_get_invariants()
16715 		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;  in tg3_get_invariants()
16717 	if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_get_invariants()
16718 	    tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_get_invariants()
16719 	    tg3_flag(tp, 57765_CLASS))  in tg3_get_invariants()
16720 		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;  in tg3_get_invariants()
16722 	if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||  in tg3_get_invariants()
16723 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {  in tg3_get_invariants()
16725 		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;  in tg3_get_invariants()
16726 		if (tg3_flag(tp, IS_NIC))  in tg3_get_invariants()
16728 			tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |  in tg3_get_invariants()
16732 	if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_invariants()
16733 		tp->grc_local_ctrl |=  in tg3_get_invariants()
16737 	tg3_pwrsrc_switch_to_vmain(tp);  in tg3_get_invariants()
16742 	if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))  in tg3_get_invariants()
16743 		tg3_flag_set(tp, JUMBO_RING_ENABLE);  in tg3_get_invariants()
16746 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16747 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_get_invariants()
16748 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||  in tg3_get_invariants()
16749 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {  in tg3_get_invariants()
16750 		tg3_flag_clear(tp, WOL_SPEED_100MB);  in tg3_get_invariants()
16752 		tg3_flag_set(tp, WOL_SPEED_100MB);  in tg3_get_invariants()
16755 	if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_invariants()
16756 		tp->phy_flags |= TG3_PHYFLG_IS_FET;  in tg3_get_invariants()
16759 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16760 	    (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_get_invariants()
16761 	     (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&  in tg3_get_invariants()
16762 	     (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||  in tg3_get_invariants()
16763 	    (tp->phy_flags & TG3_PHYFLG_IS_FET) ||  in tg3_get_invariants()
16764 	    (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_get_invariants()
16765 		tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;  in tg3_get_invariants()
16767 	if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||  in tg3_get_invariants()
16768 	    tg3_chip_rev(tp) == CHIPREV_5704_AX)  in tg3_get_invariants()
16769 		tp->phy_flags |= TG3_PHYFLG_ADC_BUG;  in tg3_get_invariants()
16770 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)  in tg3_get_invariants()
16771 		tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;  in tg3_get_invariants()
16773 	if (tg3_flag(tp, 5705_PLUS) &&  in tg3_get_invariants()
16774 	    !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&  in tg3_get_invariants()
16775 	    tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_get_invariants()
16776 	    tg3_asic_rev(tp) != ASIC_REV_57780 &&  in tg3_get_invariants()
16777 	    !tg3_flag(tp, 57765_PLUS)) {  in tg3_get_invariants()
16778 		if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_get_invariants()
16779 		    tg3_asic_rev(tp) == ASIC_REV_5787 ||  in tg3_get_invariants()
16780 		    tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_get_invariants()
16781 		    tg3_asic_rev(tp) == ASIC_REV_5761) {  in tg3_get_invariants()
16782 			if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&  in tg3_get_invariants()
16783 			    tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)  in tg3_get_invariants()
16784 				tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;  in tg3_get_invariants()
16785 			if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)  in tg3_get_invariants()
16786 				tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;  in tg3_get_invariants()
16788 			tp->phy_flags |= TG3_PHYFLG_BER_BUG;  in tg3_get_invariants()
16791 	if (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_get_invariants()
16792 	    tg3_chip_rev(tp) != CHIPREV_5784_AX) {  in tg3_get_invariants()
16793 		tp->phy_otp = tg3_read_otp_phycfg(tp);  in tg3_get_invariants()
16794 		if (tp->phy_otp == 0)  in tg3_get_invariants()
16795 			tp->phy_otp = TG3_OTP_DEFAULT;  in tg3_get_invariants()
16798 	if (tg3_flag(tp, CPMU_PRESENT))  in tg3_get_invariants()
16799 		tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;  in tg3_get_invariants()
16801 		tp->mi_mode = MAC_MI_MODE_BASE;  in tg3_get_invariants()
16803 	tp->coalesce_mode = 0;  in tg3_get_invariants()
16804 	if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&  in tg3_get_invariants()
16805 	    tg3_chip_rev(tp) != CHIPREV_5700_BX)  in tg3_get_invariants()
16806 		tp->coalesce_mode |= HOSTCC_MODE_32BYTE;  in tg3_get_invariants()
16809 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_invariants()
16810 	    tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_get_invariants()
16811 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_get_invariants()
16812 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {  in tg3_get_invariants()
16813 		tp->coalesce_mode |= HOSTCC_MODE_ATTN;  in tg3_get_invariants()
16814 		tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;  in tg3_get_invariants()
16817 	if (tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_get_invariants()
16818 	    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_get_invariants()
16819 		tg3_flag_set(tp, USE_PHYLIB);  in tg3_get_invariants()
16821 	err = tg3_mdio_init(tp);  in tg3_get_invariants()
16827 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_get_invariants()
16828 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_invariants()
16837 	tw32(GRC_MODE, val | tp->grc_mode);  in tg3_get_invariants()
16839 	tg3_switch_clocks(tp);  in tg3_get_invariants()
16847 	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,  in tg3_get_invariants()
16850 	    !tg3_flag(tp, PCIX_TARGET_HWBUG)) {  in tg3_get_invariants()
16851 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_get_invariants()
16852 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||  in tg3_get_invariants()
16853 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||  in tg3_get_invariants()
16854 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {  in tg3_get_invariants()
16861 			sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;  in tg3_get_invariants()
16867 				tg3_flag_set(tp, PCIX_TARGET_HWBUG);  in tg3_get_invariants()
16872 	tg3_nvram_init(tp);  in tg3_get_invariants()
16875 	if (tg3_asic_rev(tp) == ASIC_REV_57766 &&  in tg3_get_invariants()
16876 	    !tg3_flag(tp, NO_NVRAM))  in tg3_get_invariants()
16877 		tp->fw_needed = NULL;  in tg3_get_invariants()
16882 	if (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_get_invariants()
16885 		tg3_flag_set(tp, IS_5788);  in tg3_get_invariants()
16887 	if (!tg3_flag(tp, IS_5788) &&  in tg3_get_invariants()
16888 	    tg3_asic_rev(tp) != ASIC_REV_5700)  in tg3_get_invariants()
16889 		tg3_flag_set(tp, TAGGED_STATUS);  in tg3_get_invariants()
16890 	if (tg3_flag(tp, TAGGED_STATUS)) {  in tg3_get_invariants()
16891 		tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |  in tg3_get_invariants()
16894 		tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;  in tg3_get_invariants()
16895 		pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
16896 				       tp->misc_host_ctrl);  in tg3_get_invariants()
16900 	if (tg3_flag(tp, ENABLE_APE))  in tg3_get_invariants()
16901 		tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;  in tg3_get_invariants()
16903 		tp->mac_mode = 0;  in tg3_get_invariants()
16905 	if (tg3_10_100_only_device(tp, ent))  in tg3_get_invariants()
16906 		tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;  in tg3_get_invariants()
16908 	err = tg3_phy_probe(tp);  in tg3_get_invariants()
16910 		dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);  in tg3_get_invariants()
16912 		tg3_mdio_fini(tp);  in tg3_get_invariants()
16915 	tg3_read_vpd(tp);  in tg3_get_invariants()
16916 	tg3_read_fw_ver(tp);  in tg3_get_invariants()
16918 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_get_invariants()
16919 		tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16921 		if (tg3_asic_rev(tp) == ASIC_REV_5700)  in tg3_get_invariants()
16922 			tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16924 			tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16931 	if (tg3_asic_rev(tp) == ASIC_REV_5700)  in tg3_get_invariants()
16932 		tg3_flag_set(tp, USE_LINKCHG_REG);  in tg3_get_invariants()
16934 		tg3_flag_clear(tp, USE_LINKCHG_REG);  in tg3_get_invariants()
16940 	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&  in tg3_get_invariants()
16941 	    tg3_asic_rev(tp) == ASIC_REV_5701 &&  in tg3_get_invariants()
16942 	    !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {  in tg3_get_invariants()
16943 		tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16944 		tg3_flag_set(tp, USE_LINKCHG_REG);  in tg3_get_invariants()
16948 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_get_invariants()
16949 		tg3_flag_set(tp, POLL_SERDES);  in tg3_get_invariants()
16951 		tg3_flag_clear(tp, POLL_SERDES);  in tg3_get_invariants()
16953 	if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))  in tg3_get_invariants()
16954 		tg3_flag_set(tp, POLL_CPMU_LINK);  in tg3_get_invariants()
16956 	tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;  in tg3_get_invariants()
16957 	tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;  in tg3_get_invariants()
16958 	if (tg3_asic_rev(tp) == ASIC_REV_5701 &&  in tg3_get_invariants()
16959 	    tg3_flag(tp, PCIX_MODE)) {  in tg3_get_invariants()
16960 		tp->rx_offset = NET_SKB_PAD;  in tg3_get_invariants()
16962 		tp->rx_copy_thresh = ~(u16)0;  in tg3_get_invariants()
16966 	tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;  in tg3_get_invariants()
16967 	tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;  in tg3_get_invariants()
16968 	tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;  in tg3_get_invariants()
16970 	tp->rx_std_max_post = tp->rx_std_ring_mask + 1;  in tg3_get_invariants()
16975 	if (tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_get_invariants()
16976 	    tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_get_invariants()
16977 	    tg3_asic_rev(tp) == ASIC_REV_5755)  in tg3_get_invariants()
16978 		tp->rx_std_max_post = 8;  in tg3_get_invariants()
16980 	if (tg3_flag(tp, ASPM_WORKAROUND))  in tg3_get_invariants()
16981 		tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &  in tg3_get_invariants()
16988 static int tg3_get_macaddr_sparc(struct tg3 *tp)  in tg3_get_macaddr_sparc()  argument
16990 	struct net_device *dev = tp->dev;  in tg3_get_macaddr_sparc()
16991 	struct pci_dev *pdev = tp->pdev;  in tg3_get_macaddr_sparc()
17004 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)  in tg3_get_default_macaddr_sparc()  argument
17006 	struct net_device *dev = tp->dev;  in tg3_get_default_macaddr_sparc()
17013 static int tg3_get_device_address(struct tg3 *tp)  in tg3_get_device_address()  argument
17015 	struct net_device *dev = tp->dev;  in tg3_get_device_address()
17021 	if (!tg3_get_macaddr_sparc(tp))  in tg3_get_device_address()
17025 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_get_device_address()
17026 		err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);  in tg3_get_device_address()
17032 	if (tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_get_device_address()
17033 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_get_device_address()
17036 		if (tg3_nvram_lock(tp))  in tg3_get_device_address()
17039 			tg3_nvram_unlock(tp);  in tg3_get_device_address()
17040 	} else if (tg3_flag(tp, 5717_PLUS)) {  in tg3_get_device_address()
17041 		if (tp->pci_fn & 1)  in tg3_get_device_address()
17043 		if (tp->pci_fn > 1)  in tg3_get_device_address()
17045 	} else if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_device_address()
17049 	tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);  in tg3_get_device_address()
17054 		tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);  in tg3_get_device_address()
17065 		if (!tg3_flag(tp, NO_NVRAM) &&  in tg3_get_device_address()
17066 		    !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&  in tg3_get_device_address()
17067 		    !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {  in tg3_get_device_address()
17087 		if (!tg3_get_default_macaddr_sparc(tp))  in tg3_get_device_address()
17098 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)  in tg3_calc_dma_bndry()  argument
17104 	pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);  in tg3_calc_dma_bndry()
17113 	if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_calc_dma_bndry()
17114 	    tg3_asic_rev(tp) != ASIC_REV_5701 &&  in tg3_calc_dma_bndry()
17115 	    !tg3_flag(tp, PCI_EXPRESS))  in tg3_calc_dma_bndry()
17128 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_calc_dma_bndry()
17147 	if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {  in tg3_calc_dma_bndry()
17172 	} else if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_calc_dma_bndry()
17239 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,  in tg3_do_test_dma()  argument
17290 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,  in tg3_do_test_dma()
17292 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_do_test_dma()
17294 	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_do_test_dma()
17327 static int tg3_test_dma(struct tg3 *tp)  in tg3_test_dma()  argument
17333 	buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,  in tg3_test_dma()
17340 	tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |  in tg3_test_dma()
17343 	tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);  in tg3_test_dma()
17345 	if (tg3_flag(tp, 57765_PLUS))  in tg3_test_dma()
17348 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_test_dma()
17350 		tp->dma_rwctrl |= 0x00180000;  in tg3_test_dma()
17351 	} else if (!tg3_flag(tp, PCIX_MODE)) {  in tg3_test_dma()
17352 		if (tg3_asic_rev(tp) == ASIC_REV_5705 ||  in tg3_test_dma()
17353 		    tg3_asic_rev(tp) == ASIC_REV_5750)  in tg3_test_dma()
17354 			tp->dma_rwctrl |= 0x003f0000;  in tg3_test_dma()
17356 			tp->dma_rwctrl |= 0x003f000f;  in tg3_test_dma()
17358 		if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_test_dma()
17359 		    tg3_asic_rev(tp) == ASIC_REV_5704) {  in tg3_test_dma()
17367 			if (tg3_flag(tp, 40BIT_DMA_BUG) &&  in tg3_test_dma()
17368 			    tg3_asic_rev(tp) == ASIC_REV_5704)  in tg3_test_dma()
17369 				tp->dma_rwctrl |= 0x8000;  in tg3_test_dma()
17371 				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;  in tg3_test_dma()
17373 			if (tg3_asic_rev(tp) == ASIC_REV_5703)  in tg3_test_dma()
17376 			tp->dma_rwctrl |=  in tg3_test_dma()
17380 		} else if (tg3_asic_rev(tp) == ASIC_REV_5780) {  in tg3_test_dma()
17382 			tp->dma_rwctrl |= 0x00144000;  in tg3_test_dma()
17383 		} else if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_test_dma()
17385 			tp->dma_rwctrl |= 0x00148000;  in tg3_test_dma()
17387 			tp->dma_rwctrl |= 0x001b000f;  in tg3_test_dma()
17390 	if (tg3_flag(tp, ONE_DMA_AT_ONCE))  in tg3_test_dma()
17391 		tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;  in tg3_test_dma()
17393 	if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_test_dma()
17394 	    tg3_asic_rev(tp) == ASIC_REV_5704)  in tg3_test_dma()
17395 		tp->dma_rwctrl &= 0xfffffff0;  in tg3_test_dma()
17397 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_test_dma()
17398 	    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_test_dma()
17400 		tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;  in tg3_test_dma()
17412 		tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;  in tg3_test_dma()
17415 	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17418 	if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_test_dma()
17419 	    tg3_asic_rev(tp) != ASIC_REV_5701)  in tg3_test_dma()
17425 	saved_dma_rwctrl = tp->dma_rwctrl;  in tg3_test_dma()
17426 	tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;  in tg3_test_dma()
17427 	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17436 		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);  in tg3_test_dma()
17438 			dev_err(&tp->pdev->dev,  in tg3_test_dma()
17445 		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);  in tg3_test_dma()
17447 			dev_err(&tp->pdev->dev, "%s: Buffer read failed. "  in tg3_test_dma()
17457 			if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=  in tg3_test_dma()
17459 				tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;  in tg3_test_dma()
17460 				tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;  in tg3_test_dma()
17461 				tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17464 				dev_err(&tp->pdev->dev,  in tg3_test_dma()
17478 	if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=  in tg3_test_dma()
17485 			tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;  in tg3_test_dma()
17486 			tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;  in tg3_test_dma()
17489 			tp->dma_rwctrl = saved_dma_rwctrl;  in tg3_test_dma()
17492 		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17496 	dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);  in tg3_test_dma()
17501 static void tg3_init_bufmgr_config(struct tg3 *tp)  in tg3_init_bufmgr_config()  argument
17503 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_init_bufmgr_config()
17504 		tp->bufmgr_config.mbuf_read_dma_low_water =  in tg3_init_bufmgr_config()
17506 		tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17508 		tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17511 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =  in tg3_init_bufmgr_config()
17513 		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =  in tg3_init_bufmgr_config()
17515 		tp->bufmgr_config.mbuf_high_water_jumbo =  in tg3_init_bufmgr_config()
17517 	} else if (tg3_flag(tp, 5705_PLUS)) {  in tg3_init_bufmgr_config()
17518 		tp->bufmgr_config.mbuf_read_dma_low_water =  in tg3_init_bufmgr_config()
17520 		tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17522 		tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17524 		if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_init_bufmgr_config()
17525 			tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17527 			tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17531 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =  in tg3_init_bufmgr_config()
17533 		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =  in tg3_init_bufmgr_config()
17535 		tp->bufmgr_config.mbuf_high_water_jumbo =  in tg3_init_bufmgr_config()
17538 		tp->bufmgr_config.mbuf_read_dma_low_water =  in tg3_init_bufmgr_config()
17540 		tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17542 		tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17545 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =  in tg3_init_bufmgr_config()
17547 		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =  in tg3_init_bufmgr_config()
17549 		tp->bufmgr_config.mbuf_high_water_jumbo =  in tg3_init_bufmgr_config()
17553 	tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;  in tg3_init_bufmgr_config()
17554 	tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;  in tg3_init_bufmgr_config()
17557 static char *tg3_phy_string(struct tg3 *tp)  in tg3_phy_string()  argument
17559 	switch (tp->phy_id & TG3_PHY_ID_MASK) {  in tg3_phy_string()
17589 static char *tg3_bus_string(struct tg3 *tp, char *str)  in tg3_bus_string()  argument
17591 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_bus_string()
17594 	} else if (tg3_flag(tp, PCIX_MODE)) {  in tg3_bus_string()
17613 		if (tg3_flag(tp, PCI_HIGH_SPEED))  in tg3_bus_string()
17618 	if (tg3_flag(tp, PCI_32BIT))  in tg3_bus_string()
17625 static void tg3_init_coal(struct tg3 *tp)  in tg3_init_coal()  argument
17627 	struct ethtool_coalesce *ec = &tp->coal;  in tg3_init_coal()
17641 	if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |  in tg3_init_coal()
17649 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_init_coal()
17660 	struct tg3 *tp;  in tg3_init_one()  local
17683 	dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);  in tg3_init_one()
17691 	tp = netdev_priv(dev);  in tg3_init_one()
17692 	tp->pdev = pdev;  in tg3_init_one()
17693 	tp->dev = dev;  in tg3_init_one()
17694 	tp->rx_mode = TG3_DEF_RX_MODE;  in tg3_init_one()
17695 	tp->tx_mode = TG3_DEF_TX_MODE;  in tg3_init_one()
17696 	tp->irq_sync = 1;  in tg3_init_one()
17697 	tp->pcierr_recovery = false;  in tg3_init_one()
17700 		tp->msg_enable = tg3_debug;  in tg3_init_one()
17702 		tp->msg_enable = TG3_DEF_MSG_ENABLE;  in tg3_init_one()
17705 		tg3_flag_set(tp, IS_SSB_CORE);  in tg3_init_one()
17707 			tg3_flag_set(tp, FLUSH_POSTED_WRITES);  in tg3_init_one()
17709 			tg3_flag_set(tp, ONE_DMA_AT_ONCE);  in tg3_init_one()
17711 			tg3_flag_set(tp, USE_PHYLIB);  in tg3_init_one()
17712 			tg3_flag_set(tp, ROBOSWITCH);  in tg3_init_one()
17715 			tg3_flag_set(tp, RGMII_MODE);  in tg3_init_one()
17722 	tp->misc_host_ctrl =  in tg3_init_one()
17734 	tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |  in tg3_init_one()
17737 	tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;  in tg3_init_one()
17739 	spin_lock_init(&tp->lock);  in tg3_init_one()
17740 	spin_lock_init(&tp->indirect_lock);  in tg3_init_one()
17741 	INIT_WORK(&tp->reset_task, tg3_reset_task);  in tg3_init_one()
17743 	tp->regs = pci_ioremap_bar(pdev, BAR_0);  in tg3_init_one()
17744 	if (!tp->regs) {  in tg3_init_one()
17750 	if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||  in tg3_init_one()
17751 	    tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||  in tg3_init_one()
17752 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||  in tg3_init_one()
17753 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||  in tg3_init_one()
17754 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||  in tg3_init_one()
17755 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||  in tg3_init_one()
17756 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||  in tg3_init_one()
17757 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||  in tg3_init_one()
17758 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||  in tg3_init_one()
17759 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||  in tg3_init_one()
17760 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||  in tg3_init_one()
17761 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||  in tg3_init_one()
17762 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||  in tg3_init_one()
17763 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||  in tg3_init_one()
17764 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {  in tg3_init_one()
17765 		tg3_flag_set(tp, ENABLE_APE);  in tg3_init_one()
17766 		tp->aperegs = pci_ioremap_bar(pdev, BAR_2);  in tg3_init_one()
17767 		if (!tp->aperegs) {  in tg3_init_one()
17775 	tp->rx_pending = TG3_DEF_RX_RING_PENDING;  in tg3_init_one()
17776 	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;  in tg3_init_one()
17783 	err = tg3_get_invariants(tp, ent);  in tg3_init_one()
17796 	if (tg3_flag(tp, IS_5788))  in tg3_init_one()
17798 	else if (tg3_flag(tp, 40BIT_DMA_BUG)) {  in tg3_init_one()
17829 	tg3_init_bufmgr_config(tp);  in tg3_init_one()
17834 	if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {  in tg3_init_one()
17837 		if (tg3_flag(tp, 5755_PLUS))  in tg3_init_one()
17845 	if ((tg3_flag(tp, HW_TSO_1) ||  in tg3_init_one()
17846 	     tg3_flag(tp, HW_TSO_2) ||  in tg3_init_one()
17847 	     tg3_flag(tp, HW_TSO_3)) &&  in tg3_init_one()
17850 	if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {  in tg3_init_one()
17853 		if (tg3_flag(tp, HW_TSO_3) ||  in tg3_init_one()
17854 		    tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_init_one()
17855 		    (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_init_one()
17856 		     tg3_chip_rev(tp) != CHIPREV_5784_AX) ||  in tg3_init_one()
17857 		    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_init_one()
17858 		    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_init_one()
17871 	if (tg3_asic_rev(tp) != ASIC_REV_5780 &&  in tg3_init_one()
17872 	    !tg3_flag(tp, CPMU_PRESENT))  in tg3_init_one()
17881 	dev->max_mtu = TG3_MAX_MTU(tp);  in tg3_init_one()
17883 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&  in tg3_init_one()
17884 	    !tg3_flag(tp, TSO_CAPABLE) &&  in tg3_init_one()
17886 		tg3_flag_set(tp, MAX_RXPEND_64);  in tg3_init_one()
17887 		tp->rx_pending = 63;  in tg3_init_one()
17890 	err = tg3_get_device_address(tp);  in tg3_init_one()
17900 	for (i = 0; i < tp->irq_max; i++) {  in tg3_init_one()
17901 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_init_one()
17903 		tnapi->tp = tp;  in tg3_init_one()
17920 		if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_init_one()
17948 		tg3_full_lock(tp, 0);  in tg3_init_one()
17950 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_init_one()
17951 		tg3_full_unlock(tp);  in tg3_init_one()
17954 	err = tg3_test_dma(tp);  in tg3_init_one()
17960 	tg3_init_coal(tp);  in tg3_init_one()
17964 	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_init_one()
17965 	    tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_init_one()
17966 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_init_one()
17967 		tg3_flag_set(tp, PTP_CAPABLE);  in tg3_init_one()
17969 	tg3_timer_init(tp);  in tg3_init_one()
17971 	tg3_carrier_off(tp);  in tg3_init_one()
17979 	if (tg3_flag(tp, PTP_CAPABLE)) {  in tg3_init_one()
17980 		tg3_ptp_init(tp);  in tg3_init_one()
17981 		tp->ptp_clock = ptp_clock_register(&tp->ptp_info,  in tg3_init_one()
17982 						   &tp->pdev->dev);  in tg3_init_one()
17983 		if (IS_ERR(tp->ptp_clock))  in tg3_init_one()
17984 			tp->ptp_clock = NULL;  in tg3_init_one()
17988 		    tp->board_part_number,  in tg3_init_one()
17989 		    tg3_chip_rev_id(tp),  in tg3_init_one()
17990 		    tg3_bus_string(tp, str),  in tg3_init_one()
17993 	if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {  in tg3_init_one()
17996 		if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)  in tg3_init_one()
17998 		else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_init_one()
18005 			    tg3_phy_string(tp), ethtype,  in tg3_init_one()
18006 			    (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,  in tg3_init_one()
18007 			    (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);  in tg3_init_one()
18012 		    tg3_flag(tp, USE_LINKCHG_REG) != 0,  in tg3_init_one()
18013 		    (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,  in tg3_init_one()
18014 		    tg3_flag(tp, ENABLE_ASF) != 0,  in tg3_init_one()
18015 		    tg3_flag(tp, TSO_CAPABLE) != 0);  in tg3_init_one()
18017 		    tp->dma_rwctrl,  in tg3_init_one()
18026 	if (tp->aperegs) {  in tg3_init_one()
18027 		iounmap(tp->aperegs);  in tg3_init_one()
18028 		tp->aperegs = NULL;  in tg3_init_one()
18032 	if (tp->regs) {  in tg3_init_one()
18033 		iounmap(tp->regs);  in tg3_init_one()
18034 		tp->regs = NULL;  in tg3_init_one()
18054 		struct tg3 *tp = netdev_priv(dev);  in tg3_remove_one()  local
18056 		tg3_ptp_fini(tp);  in tg3_remove_one()
18058 		release_firmware(tp->fw);  in tg3_remove_one()
18060 		tg3_reset_task_cancel(tp);  in tg3_remove_one()
18062 		if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_remove_one()
18063 			tg3_phy_fini(tp);  in tg3_remove_one()
18064 			tg3_mdio_fini(tp);  in tg3_remove_one()
18068 		if (tp->aperegs) {  in tg3_remove_one()
18069 			iounmap(tp->aperegs);  in tg3_remove_one()
18070 			tp->aperegs = NULL;  in tg3_remove_one()
18072 		if (tp->regs) {  in tg3_remove_one()
18073 			iounmap(tp->regs);  in tg3_remove_one()
18074 			tp->regs = NULL;  in tg3_remove_one()
18087 	struct tg3 *tp = netdev_priv(dev);  in tg3_suspend()  local
18095 	tg3_reset_task_cancel(tp);  in tg3_suspend()
18096 	tg3_phy_stop(tp);  in tg3_suspend()
18097 	tg3_netif_stop(tp);  in tg3_suspend()
18099 	tg3_timer_stop(tp);  in tg3_suspend()
18101 	tg3_full_lock(tp, 1);  in tg3_suspend()
18102 	tg3_disable_ints(tp);  in tg3_suspend()
18103 	tg3_full_unlock(tp);  in tg3_suspend()
18107 	tg3_full_lock(tp, 0);  in tg3_suspend()
18108 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_suspend()
18109 	tg3_flag_clear(tp, INIT_COMPLETE);  in tg3_suspend()
18110 	tg3_full_unlock(tp);  in tg3_suspend()
18112 	err = tg3_power_down_prepare(tp);  in tg3_suspend()
18116 		tg3_full_lock(tp, 0);  in tg3_suspend()
18118 		tg3_flag_set(tp, INIT_COMPLETE);  in tg3_suspend()
18119 		err2 = tg3_restart_hw(tp, true);  in tg3_suspend()
18123 		tg3_timer_start(tp);  in tg3_suspend()
18126 		tg3_netif_start(tp);  in tg3_suspend()
18129 		tg3_full_unlock(tp);  in tg3_suspend()
18132 			tg3_phy_start(tp);  in tg3_suspend()
18144 	struct tg3 *tp = netdev_priv(dev);  in tg3_resume()  local
18154 	tg3_full_lock(tp, 0);  in tg3_resume()
18156 	tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_resume()
18158 	tg3_flag_set(tp, INIT_COMPLETE);  in tg3_resume()
18159 	err = tg3_restart_hw(tp,  in tg3_resume()
18160 			     !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));  in tg3_resume()
18164 	tg3_timer_start(tp);  in tg3_resume()
18166 	tg3_netif_start(tp);  in tg3_resume()
18169 	tg3_full_unlock(tp);  in tg3_resume()
18172 		tg3_phy_start(tp);  in tg3_resume()
18185 	struct tg3 *tp = netdev_priv(dev);  in tg3_shutdown()  local
18194 		tg3_power_down(tp);  in tg3_shutdown()
18211 	struct tg3 *tp = netdev_priv(netdev);  in tg3_io_error_detected()  local
18224 		tp->pcierr_recovery = true;  in tg3_io_error_detected()
18226 	tg3_phy_stop(tp);  in tg3_io_error_detected()
18228 	tg3_netif_stop(tp);  in tg3_io_error_detected()
18230 	tg3_timer_stop(tp);  in tg3_io_error_detected()
18233 	tg3_reset_task_cancel(tp);  in tg3_io_error_detected()
18238 	tg3_full_lock(tp, 0);  in tg3_io_error_detected()
18239 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);  in tg3_io_error_detected()
18240 	tg3_full_unlock(tp);  in tg3_io_error_detected()
18245 			tg3_napi_enable(tp);  in tg3_io_error_detected()
18270 	struct tg3 *tp = netdev_priv(netdev);  in tg3_io_slot_reset()  local
18291 	err = tg3_power_up(tp);  in tg3_io_slot_reset()
18299 		tg3_napi_enable(tp);  in tg3_io_slot_reset()
18317 	struct tg3 *tp = netdev_priv(netdev);  in tg3_io_resume()  local
18325 	tg3_full_lock(tp, 0);  in tg3_io_resume()
18326 	tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_io_resume()
18327 	tg3_flag_set(tp, INIT_COMPLETE);  in tg3_io_resume()
18328 	err = tg3_restart_hw(tp, true);  in tg3_io_resume()
18330 		tg3_full_unlock(tp);  in tg3_io_resume()
18337 	tg3_timer_start(tp);  in tg3_io_resume()
18339 	tg3_netif_start(tp);  in tg3_io_resume()
18341 	tg3_full_unlock(tp);  in tg3_io_resume()
18343 	tg3_phy_start(tp);  in tg3_io_resume()
18346 	tp->pcierr_recovery = false;  in tg3_io_resume()