Lines Matching refs:tg3_writephy
1240 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() function
1249 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1253 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1257 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1262 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1272 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1276 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1280 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1295 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1306 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1308 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1317 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1331 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1357 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1370 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
2225 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2232 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2234 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2283 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2290 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2292 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2491 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2496 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2499 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2505 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2507 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2532 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2533 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2534 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2551 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2553 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2555 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2556 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2584 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2587 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2594 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2615 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2616 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2620 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2627 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2728 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2729 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2741 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2743 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2744 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2747 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2772 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2778 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
3106 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3107 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3110 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3114 tg3_writephy(tp, in tg3_power_down_phy()
3118 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3123 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3146 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
4341 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4352 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4457 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4471 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4494 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4507 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4853 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4854 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4855 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4856 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4864 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4866 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4871 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4874 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
5469 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5472 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5480 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5483 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5485 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5486 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5489 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5491 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5493 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5495 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5505 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5907 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5909 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5940 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5941 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5947 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
6032 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6036 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6049 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6059 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6067 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
8230 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8234 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8239 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8249 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8280 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
10701 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
11806 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
12394 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
15619 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()