Lines Matching refs:tg3_phy_auxctl_write
1326 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() function
1349 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
2198 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2211 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2304 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2320 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2757 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2763 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
3129 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
4142 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4616 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4801 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4888 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()