14387 	u32 nvcfg1;  in tg3_get_nvram_info()  local
14389 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_nvram_info()
14390 	if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {  in tg3_get_nvram_info()
14393 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_nvram_info()
14394 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_nvram_info()
14399 		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {  in tg3_get_nvram_info()
14465 	u32 nvcfg1;  in tg3_get_5752_nvram_info()  local
14467 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5752_nvram_info()
14470 	if (nvcfg1 & (1 << 27))  in tg3_get_5752_nvram_info()
14473 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5752_nvram_info()
14494 		tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5752_nvram_info()
14499 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5752_nvram_info()
14500 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5752_nvram_info()
14506 	u32 nvcfg1, protect = 0;  in tg3_get_5755_nvram_info()  local
14508 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5755_nvram_info()
14511 	if (nvcfg1 & (1 << 27)) {  in tg3_get_5755_nvram_info()
14516 	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5755_nvram_info()
14517 	switch (nvcfg1) {  in tg3_get_5755_nvram_info()
14526 		if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||  in tg3_get_5755_nvram_info()
14527 		    nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)  in tg3_get_5755_nvram_info()
14530 		else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)  in tg3_get_5755_nvram_info()
14544 		if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)  in tg3_get_5755_nvram_info()
14548 		else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)  in tg3_get_5755_nvram_info()
14562 	u32 nvcfg1;  in tg3_get_5787_nvram_info()  local
14564 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5787_nvram_info()
14566 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5787_nvram_info()
14575 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5787_nvram_info()
14576 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5787_nvram_info()
14600 	u32 nvcfg1, protect = 0;  in tg3_get_5761_nvram_info()  local
14602 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5761_nvram_info()
14605 	if (nvcfg1 & (1 << 27)) {  in tg3_get_5761_nvram_info()
14610 	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5761_nvram_info()
14611 	switch (nvcfg1) {  in tg3_get_5761_nvram_info()
14644 		switch (nvcfg1) {  in tg3_get_5761_nvram_info()
14682 	u32 nvcfg1;  in tg3_get_57780_nvram_info()  local
14684 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_57780_nvram_info()
14686 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14693 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_57780_nvram_info()
14694 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_57780_nvram_info()
14707 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14730 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14747 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_57780_nvram_info()
14755 	u32 nvcfg1;  in tg3_get_5717_nvram_info()  local
14757 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5717_nvram_info()
14759 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14766 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5717_nvram_info()
14767 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5717_nvram_info()
14780 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14807 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14826 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5717_nvram_info()
14833 	u32 nvcfg1, nvmpinstrp, nv_status;  in tg3_get_5720_nvram_info()  local
14835 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5720_nvram_info()
14836 	nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5720_nvram_info()
14839 		if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {  in tg3_get_5720_nvram_info()
14883 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5720_nvram_info()
14884 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5720_nvram_info()
14979 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5720_nvram_info()