13106 #define TG3_FL_NOT_5705	0x2  in tg3_test_registers()  macro
13113 		{ MAC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13117 		{ MAC_STATUS, TG3_FL_NOT_5705,  in tg3_test_registers()
13131 		{ MAC_RX_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13145 		{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,  in tg3_test_registers()
13147 		{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13149 		{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,  in tg3_test_registers()
13151 		{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,  in tg3_test_registers()
13163 		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13167 		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13171 		{ HOSTCC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13175 		{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13179 		{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13183 		{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13187 		{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13191 		{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13193 		{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13195 		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13199 		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13203 		{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13205 		{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13207 		{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13229 		{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13231 		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,  in tg3_test_registers()
13237 		{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13255 		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))  in tg3_test_registers()