1944 	u32 wb_data[2];  in bnx2x_update_pfc_bmac1()  local
1955 	wb_data[0] = val;  in bnx2x_update_pfc_bmac1()
1956 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac1()
1957 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac1()
1965 	wb_data[0] = val;  in bnx2x_update_pfc_bmac1()
1966 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac1()
1967 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac1()
1977 	u32 wb_data[2];  in bnx2x_update_pfc_bmac2()  local
1988 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
1989 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
1990 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
1999 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2000 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2001 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2006 		wb_data[0] = 0x0;  in bnx2x_update_pfc_bmac2()
2007 		wb_data[0] |= (1<<0);  /* RX */  in bnx2x_update_pfc_bmac2()
2008 		wb_data[0] |= (1<<1);  /* TX */  in bnx2x_update_pfc_bmac2()
2009 		wb_data[0] |= (1<<2);  /* Force initial Xon */  in bnx2x_update_pfc_bmac2()
2010 		wb_data[0] |= (1<<3);  /* 8 cos */  in bnx2x_update_pfc_bmac2()
2011 		wb_data[0] |= (1<<5);  /* STATS */  in bnx2x_update_pfc_bmac2()
2012 		wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2014 			    wb_data, 2);  in bnx2x_update_pfc_bmac2()
2016 		wb_data[0] &= ~(1<<2);  in bnx2x_update_pfc_bmac2()
2020 		wb_data[0] = 0x8;  in bnx2x_update_pfc_bmac2()
2021 		wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2024 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2035 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2036 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2038 		    wb_data, 2);  in bnx2x_update_pfc_bmac2()
2050 	wb_data[0] = val;  in bnx2x_update_pfc_bmac2()
2051 	wb_data[1] = 0;  in bnx2x_update_pfc_bmac2()
2052 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_update_pfc_bmac2()
2280 	u32 wb_data[2];  in bnx2x_bmac1_enable()  local
2286 	wb_data[0] = 0x3c;  in bnx2x_bmac1_enable()
2287 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2289 		    wb_data, 2);  in bnx2x_bmac1_enable()
2292 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac1_enable()
2296 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac1_enable()
2298 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);  in bnx2x_bmac1_enable()
2306 	wb_data[0] = val;  in bnx2x_bmac1_enable()
2307 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2308 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_bmac1_enable()
2311 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;  in bnx2x_bmac1_enable()
2312 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2313 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2318 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;  in bnx2x_bmac1_enable()
2319 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2320 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2323 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;  in bnx2x_bmac1_enable()
2324 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2325 	REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);  in bnx2x_bmac1_enable()
2328 	wb_data[0] = 0x1000200;  in bnx2x_bmac1_enable()
2329 	wb_data[1] = 0;  in bnx2x_bmac1_enable()
2331 		    wb_data, 2);  in bnx2x_bmac1_enable()
2344 	u32 wb_data[2];  in bnx2x_bmac2_enable()  local
2348 	wb_data[0] = 0;  in bnx2x_bmac2_enable()
2349 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2350 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);  in bnx2x_bmac2_enable()
2354 	wb_data[0] = 0x3c;  in bnx2x_bmac2_enable()
2355 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2357 		    wb_data, 2);  in bnx2x_bmac2_enable()
2362 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac2_enable()
2366 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac2_enable()
2369 		    wb_data, 2);  in bnx2x_bmac2_enable()
2374 	wb_data[0] = 0x1000200;  in bnx2x_bmac2_enable()
2375 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2377 		    wb_data, 2);  in bnx2x_bmac2_enable()
2381 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;  in bnx2x_bmac2_enable()
2382 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2383 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2387 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD;  in bnx2x_bmac2_enable()
2388 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2389 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2392 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2;  in bnx2x_bmac2_enable()
2393 	wb_data[1] = 0;  in bnx2x_bmac2_enable()
2394 	REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);  in bnx2x_bmac2_enable()
2450 	u32 wb_data[2];  in bnx2x_set_bmac_rx()  local
2462 		REG_RD_DMAE(bp, bmac_addr, wb_data, 2);  in bnx2x_set_bmac_rx()
2464 			wb_data[0] |= BMAC_CONTROL_RX_ENABLE;  in bnx2x_set_bmac_rx()
2466 			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;  in bnx2x_set_bmac_rx()
2467 		REG_WR_DMAE(bp, bmac_addr, wb_data, 2);  in bnx2x_set_bmac_rx()
13778 		u32 wb_data[2];  in bnx2x_check_half_open_conn()  local
13787 		REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);  in bnx2x_check_half_open_conn()
13788 		lss_status = (wb_data[0] > 0);  in bnx2x_check_half_open_conn()