1455 				   params->phy[phy_index].mdio_ctrl);  in bnx2x_set_mdio_emac_per_phy()
2600 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2601 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_write()
2608 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl22_write()
2613 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2623 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_write()
2636 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2637 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_read()
2644 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl22_read()
2649 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2662 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_read()
2679 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_read()
2683 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2689 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2694 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2710 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2715 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2739 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2754 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_write()
2758 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
2765 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2770 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2785 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2790 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2812 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
8298 	fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in bnx2x_verify_sfp_module()
11634 	.mdio_ctrl	= 0,
11660 	.mdio_ctrl	= 0,
11695 	.mdio_ctrl	= 0,
11730 	.mdio_ctrl	= 0,
11770 	.mdio_ctrl	= 0,
11799 	.mdio_ctrl	= 0,
11830 	.mdio_ctrl	= 0,
11858 	.mdio_ctrl	= 0,
11889 	.mdio_ctrl	= 0,
11921 	.mdio_ctrl	= 0,
11951 	.mdio_ctrl	= 0,
11988 	.mdio_ctrl	= 0,
12025 	.mdio_ctrl	= 0,
12059 	.mdio_ctrl	= 0,
12093 	.mdio_ctrl	= 0,
12126 	.mdio_ctrl	= 0,
12339 	phy->mdio_ctrl = bnx2x_get_emac_base(bp,  in bnx2x_populate_int_phy()
12348 		   port, phy->addr, phy->mdio_ctrl);  in bnx2x_populate_int_phy()
12462 	phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);  in bnx2x_populate_ext_phy()
12478 		   phy->addr, phy->mdio_ctrl);  in bnx2x_populate_ext_phy()