250 static void bnx2_init_napi(struct bnx2 *bp);
251 static void bnx2_del_napi(struct bnx2 *bp);
253 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)  in bnx2_tx_avail()  argument
266 	return bp->tx_ring_size - diff;  in bnx2_tx_avail()
270 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)  in bnx2_reg_rd_ind()  argument
275 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_reg_rd_ind()
276 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
277 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
278 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_reg_rd_ind()
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_reg_wr_ind()  argument
287 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_reg_wr_ind()
288 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
289 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
290 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_reg_wr_ind()
294 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_shmem_wr()  argument
296 	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);  in bnx2_shmem_wr()
300 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)  in bnx2_shmem_rd()  argument
302 	return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);  in bnx2_shmem_rd()
306 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)  in bnx2_ctx_wr()  argument
311 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_ctx_wr()
312 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_ctx_wr()
315 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
316 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
319 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
325 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
326 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
328 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_ctx_wr()
335 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_drv_ctl()  local
340 		bnx2_reg_wr_ind(bp, io->offset, io->data);  in bnx2_drv_ctl()
343 		io->data = bnx2_reg_rd_ind(bp, io->offset);  in bnx2_drv_ctl()
346 		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);  in bnx2_drv_ctl()
354 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)  in bnx2_setup_cnic_irq_info()  argument
356 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_setup_cnic_irq_info()
357 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_setup_cnic_irq_info()
360 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_setup_cnic_irq_info()
363 		sb_id = bp->irq_nvecs;  in bnx2_setup_cnic_irq_info()
373 	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;  in bnx2_setup_cnic_irq_info()
384 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_register_cnic()  local
385 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_register_cnic()
393 	if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))  in bnx2_register_cnic()
396 	bp->cnic_data = data;  in bnx2_register_cnic()
397 	rcu_assign_pointer(bp->cnic_ops, ops);  in bnx2_register_cnic()
402 	bnx2_setup_cnic_irq_info(bp);  in bnx2_register_cnic()
409 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_unregister_cnic()  local
410 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_unregister_cnic()
411 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_unregister_cnic()
413 	mutex_lock(&bp->cnic_lock);  in bnx2_unregister_cnic()
416 	RCU_INIT_POINTER(bp->cnic_ops, NULL);  in bnx2_unregister_cnic()
417 	mutex_unlock(&bp->cnic_lock);  in bnx2_unregister_cnic()
424 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_cnic_probe()  local
425 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_cnic_probe()
431 	cp->chip_id = bp->chip_id;  in bnx2_cnic_probe()
432 	cp->pdev = bp->pdev;  in bnx2_cnic_probe()
433 	cp->io_base = bp->regview;  in bnx2_cnic_probe()
442 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
447 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_stop()
448 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_stop()
449 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_stop()
452 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_stop()
454 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_stop()
458 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
463 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_start()
464 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_start()
465 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_start()
467 		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_cnic_start()
468 			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_cnic_start()
473 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_start()
475 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_start()
481 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
486 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
493 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)  in bnx2_read_phy()  argument
498 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
499 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
502 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
503 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
508 	val1 = (bp->phy_addr << 21) | (reg << 16) |  in bnx2_read_phy()
511 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
516 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
520 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
536 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
537 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
540 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
541 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
550 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)  in bnx2_write_phy()  argument
555 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
556 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
559 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
560 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
565 	val1 = (bp->phy_addr << 21) | (reg << 16) | val |  in bnx2_write_phy()
568 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
573 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
585 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
586 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
589 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
590 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
599 bnx2_disable_int(struct bnx2 *bp)  in bnx2_disable_int()  argument
604 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_disable_int()
605 		bnapi = &bp->bnx2_napi[i];  in bnx2_disable_int()
606 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
609 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
613 bnx2_enable_int(struct bnx2 *bp)  in bnx2_enable_int()  argument
618 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_enable_int()
619 		bnapi = &bp->bnx2_napi[i];  in bnx2_enable_int()
621 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
626 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
630 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
634 bnx2_disable_int_sync(struct bnx2 *bp)  in bnx2_disable_int_sync()  argument
638 	atomic_inc(&bp->intr_sem);  in bnx2_disable_int_sync()
639 	if (!netif_running(bp->dev))  in bnx2_disable_int_sync()
642 	bnx2_disable_int(bp);  in bnx2_disable_int_sync()
643 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_disable_int_sync()
644 		synchronize_irq(bp->irq_tbl[i].vector);  in bnx2_disable_int_sync()
648 bnx2_napi_disable(struct bnx2 *bp)  in bnx2_napi_disable()  argument
652 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_disable()
653 		napi_disable(&bp->bnx2_napi[i].napi);  in bnx2_napi_disable()
657 bnx2_napi_enable(struct bnx2 *bp)  in bnx2_napi_enable()  argument
661 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_enable()
662 		napi_enable(&bp->bnx2_napi[i].napi);  in bnx2_napi_enable()
666 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)  in bnx2_netif_stop()  argument
669 		bnx2_cnic_stop(bp);  in bnx2_netif_stop()
670 	if (netif_running(bp->dev)) {  in bnx2_netif_stop()
671 		bnx2_napi_disable(bp);  in bnx2_netif_stop()
672 		netif_tx_disable(bp->dev);  in bnx2_netif_stop()
674 	bnx2_disable_int_sync(bp);  in bnx2_netif_stop()
675 	netif_carrier_off(bp->dev);	/* prevent tx timeout */  in bnx2_netif_stop()
679 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)  in bnx2_netif_start()  argument
681 	if (atomic_dec_and_test(&bp->intr_sem)) {  in bnx2_netif_start()
682 		if (netif_running(bp->dev)) {  in bnx2_netif_start()
683 			netif_tx_wake_all_queues(bp->dev);  in bnx2_netif_start()
684 			spin_lock_bh(&bp->phy_lock);  in bnx2_netif_start()
685 			if (bp->link_up)  in bnx2_netif_start()
686 				netif_carrier_on(bp->dev);  in bnx2_netif_start()
687 			spin_unlock_bh(&bp->phy_lock);  in bnx2_netif_start()
688 			bnx2_napi_enable(bp);  in bnx2_netif_start()
689 			bnx2_enable_int(bp);  in bnx2_netif_start()
691 				bnx2_cnic_start(bp);  in bnx2_netif_start()
697 bnx2_free_tx_mem(struct bnx2 *bp)  in bnx2_free_tx_mem()  argument
701 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_mem()
702 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_mem()
706 			dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_free_tx_mem()
717 bnx2_free_rx_mem(struct bnx2 *bp)  in bnx2_free_rx_mem()  argument
721 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_mem()
722 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_mem()
726 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_free_rx_mem()
728 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
736 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_free_rx_mem()
738 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
749 bnx2_alloc_tx_mem(struct bnx2 *bp)  in bnx2_alloc_tx_mem()  argument
753 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_alloc_tx_mem()
754 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_tx_mem()
762 			dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_alloc_tx_mem()
771 bnx2_alloc_rx_mem(struct bnx2 *bp)  in bnx2_alloc_rx_mem()  argument
775 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_alloc_rx_mem()
776 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_rx_mem()
781 			vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));  in bnx2_alloc_rx_mem()
785 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_alloc_rx_mem()
787 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
796 		if (bp->rx_pg_ring_size) {  in bnx2_alloc_rx_mem()
799 						   bp->rx_max_pg_ring));  in bnx2_alloc_rx_mem()
805 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_alloc_rx_mem()
807 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
822 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_free_stats_blk()  local
824 	if (bp->status_blk) {  in bnx2_free_stats_blk()
825 		dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_free_stats_blk()
826 				  bp->status_blk,  in bnx2_free_stats_blk()
827 				  bp->status_blk_mapping);  in bnx2_free_stats_blk()
828 		bp->status_blk = NULL;  in bnx2_free_stats_blk()
829 		bp->stats_blk = NULL;  in bnx2_free_stats_blk()
838 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_alloc_stats_blk()  local
842 	if (bp->flags & BNX2_FLAG_MSIX_CAP)  in bnx2_alloc_stats_blk()
845 	bp->status_stats_size = status_blk_size +  in bnx2_alloc_stats_blk()
847 	status_blk = dma_zalloc_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_alloc_stats_blk()
848 					 &bp->status_blk_mapping, GFP_KERNEL);  in bnx2_alloc_stats_blk()
852 	bp->status_blk = status_blk;  in bnx2_alloc_stats_blk()
853 	bp->stats_blk = status_blk + status_blk_size;  in bnx2_alloc_stats_blk()
854 	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;  in bnx2_alloc_stats_blk()
860 bnx2_free_mem(struct bnx2 *bp)  in bnx2_free_mem()  argument
863 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_free_mem()
865 	bnx2_free_tx_mem(bp);  in bnx2_free_mem()
866 	bnx2_free_rx_mem(bp);  in bnx2_free_mem()
868 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_free_mem()
869 		if (bp->ctx_blk[i]) {  in bnx2_free_mem()
870 			dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,  in bnx2_free_mem()
871 					  bp->ctx_blk[i],  in bnx2_free_mem()
872 					  bp->ctx_blk_mapping[i]);  in bnx2_free_mem()
873 			bp->ctx_blk[i] = NULL;  in bnx2_free_mem()
882 bnx2_alloc_mem(struct bnx2 *bp)  in bnx2_alloc_mem()  argument
887 	bnapi = &bp->bnx2_napi[0];  in bnx2_alloc_mem()
888 	bnapi->status_blk.msi = bp->status_blk;  in bnx2_alloc_mem()
893 	if (bp->flags & BNX2_FLAG_MSIX_CAP) {  in bnx2_alloc_mem()
894 		for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_alloc_mem()
897 			bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_mem()
899 			sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);  in bnx2_alloc_mem()
909 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_alloc_mem()
910 		bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;  in bnx2_alloc_mem()
911 		if (bp->ctx_pages == 0)  in bnx2_alloc_mem()
912 			bp->ctx_pages = 1;  in bnx2_alloc_mem()
913 		for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_alloc_mem()
914 			bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_mem()
916 						&bp->ctx_blk_mapping[i],  in bnx2_alloc_mem()
918 			if (!bp->ctx_blk[i])  in bnx2_alloc_mem()
923 	err = bnx2_alloc_rx_mem(bp);  in bnx2_alloc_mem()
927 	err = bnx2_alloc_tx_mem(bp);  in bnx2_alloc_mem()
934 	bnx2_free_mem(bp);  in bnx2_alloc_mem()
939 bnx2_report_fw_link(struct bnx2 *bp)  in bnx2_report_fw_link()  argument
943 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_report_fw_link()
946 	if (bp->link_up) {  in bnx2_report_fw_link()
949 		switch (bp->line_speed) {  in bnx2_report_fw_link()
951 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
957 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
963 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
969 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
978 		if (bp->autoneg) {  in bnx2_report_fw_link()
981 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
982 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
985 			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)  in bnx2_report_fw_link()
994 	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);  in bnx2_report_fw_link()
998 bnx2_xceiver_str(struct bnx2 *bp)  in bnx2_xceiver_str()  argument
1000 	return (bp->phy_port == PORT_FIBRE) ? "SerDes" :  in bnx2_xceiver_str()
1001 		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :  in bnx2_xceiver_str()
1006 bnx2_report_link(struct bnx2 *bp)  in bnx2_report_link()  argument
1008 	if (bp->link_up) {  in bnx2_report_link()
1009 		netif_carrier_on(bp->dev);  in bnx2_report_link()
1010 		netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",  in bnx2_report_link()
1011 			    bnx2_xceiver_str(bp),  in bnx2_report_link()
1012 			    bp->line_speed,  in bnx2_report_link()
1013 			    bp->duplex == DUPLEX_FULL ? "full" : "half");  in bnx2_report_link()
1015 		if (bp->flow_ctrl) {  in bnx2_report_link()
1016 			if (bp->flow_ctrl & FLOW_CTRL_RX) {  in bnx2_report_link()
1018 				if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_report_link()
1028 		netif_carrier_off(bp->dev);  in bnx2_report_link()
1029 		netdev_err(bp->dev, "NIC %s Link is Down\n",  in bnx2_report_link()
1030 			   bnx2_xceiver_str(bp));  in bnx2_report_link()
1033 	bnx2_report_fw_link(bp);  in bnx2_report_link()
1037 bnx2_resolve_flow_ctrl(struct bnx2 *bp)  in bnx2_resolve_flow_ctrl()  argument
1041 	bp->flow_ctrl = 0;  in bnx2_resolve_flow_ctrl()
1042 	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_resolve_flow_ctrl()
1045 		if (bp->duplex == DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1046 			bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_resolve_flow_ctrl()
1051 	if (bp->duplex != DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1055 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_resolve_flow_ctrl()
1056 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_resolve_flow_ctrl()
1059 		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_resolve_flow_ctrl()
1061 			bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1063 			bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1067 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_resolve_flow_ctrl()
1068 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_resolve_flow_ctrl()
1070 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_resolve_flow_ctrl()
1091 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1094 				bp->flow_ctrl = FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1099 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1107 			bp->flow_ctrl = FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1113 bnx2_5709s_linkup(struct bnx2 *bp)  in bnx2_5709s_linkup()  argument
1117 	bp->link_up = 1;  in bnx2_5709s_linkup()
1119 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);  in bnx2_5709s_linkup()
1120 	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);  in bnx2_5709s_linkup()
1121 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_5709s_linkup()
1123 	if ((bp->autoneg & AUTONEG_SPEED) == 0) {  in bnx2_5709s_linkup()
1124 		bp->line_speed = bp->req_line_speed;  in bnx2_5709s_linkup()
1125 		bp->duplex = bp->req_duplex;  in bnx2_5709s_linkup()
1131 			bp->line_speed = SPEED_10;  in bnx2_5709s_linkup()
1134 			bp->line_speed = SPEED_100;  in bnx2_5709s_linkup()
1138 			bp->line_speed = SPEED_1000;  in bnx2_5709s_linkup()
1141 			bp->line_speed = SPEED_2500;  in bnx2_5709s_linkup()
1145 		bp->duplex = DUPLEX_FULL;  in bnx2_5709s_linkup()
1147 		bp->duplex = DUPLEX_HALF;  in bnx2_5709s_linkup()
1152 bnx2_5708s_linkup(struct bnx2 *bp)  in bnx2_5708s_linkup()  argument
1156 	bp->link_up = 1;  in bnx2_5708s_linkup()
1157 	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_5708s_linkup()
1160 			bp->line_speed = SPEED_10;  in bnx2_5708s_linkup()
1163 			bp->line_speed = SPEED_100;  in bnx2_5708s_linkup()
1166 			bp->line_speed = SPEED_1000;  in bnx2_5708s_linkup()
1169 			bp->line_speed = SPEED_2500;  in bnx2_5708s_linkup()
1173 		bp->duplex = DUPLEX_FULL;  in bnx2_5708s_linkup()
1175 		bp->duplex = DUPLEX_HALF;  in bnx2_5708s_linkup()
1181 bnx2_5706s_linkup(struct bnx2 *bp)  in bnx2_5706s_linkup()  argument
1185 	bp->link_up = 1;  in bnx2_5706s_linkup()
1186 	bp->line_speed = SPEED_1000;  in bnx2_5706s_linkup()
1188 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706s_linkup()
1190 		bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1193 		bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1200 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_5706s_linkup()
1201 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_5706s_linkup()
1207 			bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1210 			bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1218 bnx2_copper_linkup(struct bnx2 *bp)  in bnx2_copper_linkup()  argument
1222 	bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1224 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_copper_linkup()
1228 		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);  in bnx2_copper_linkup()
1229 		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);  in bnx2_copper_linkup()
1233 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1234 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1237 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1238 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1241 			bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_copper_linkup()
1242 			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_copper_linkup()
1246 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1247 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1250 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1251 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1254 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1255 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1258 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1259 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1262 				bp->line_speed = 0;  in bnx2_copper_linkup()
1263 				bp->link_up = 0;  in bnx2_copper_linkup()
1269 			bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1272 			bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1275 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1278 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1282 	if (bp->link_up) {  in bnx2_copper_linkup()
1285 		bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);  in bnx2_copper_linkup()
1287 			bp->phy_flags |= BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1294 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)  in bnx2_init_rx_context()  argument
1302 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_init_rx_context()
1305 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);  in bnx2_init_rx_context()
1309 bnx2_init_all_rx_contexts(struct bnx2 *bp)  in bnx2_init_all_rx_contexts()  argument
1314 	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {  in bnx2_init_all_rx_contexts()
1317 		bnx2_init_rx_context(bp, cid);  in bnx2_init_all_rx_contexts()
1322 bnx2_set_mac_link(struct bnx2 *bp)  in bnx2_set_mac_link()  argument
1326 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1327 	if (bp->link_up && (bp->line_speed == SPEED_1000) &&  in bnx2_set_mac_link()
1328 		(bp->duplex == DUPLEX_HALF)) {  in bnx2_set_mac_link()
1329 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1333 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1339 	if (bp->link_up) {  in bnx2_set_mac_link()
1340 		switch (bp->line_speed) {  in bnx2_set_mac_link()
1342 				if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {  in bnx2_set_mac_link()
1363 	if (bp->duplex == DUPLEX_HALF)  in bnx2_set_mac_link()
1365 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1368 	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1370 	if (bp->flow_ctrl & FLOW_CTRL_RX)  in bnx2_set_mac_link()
1371 		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1372 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1375 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1378 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_set_mac_link()
1380 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1383 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1385 	bnx2_init_all_rx_contexts(bp);  in bnx2_set_mac_link()
1389 bnx2_enable_bmsr1(struct bnx2 *bp)  in bnx2_enable_bmsr1()  argument
1391 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_enable_bmsr1()
1392 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_enable_bmsr1()
1393 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_bmsr1()
1398 bnx2_disable_bmsr1(struct bnx2 *bp)  in bnx2_disable_bmsr1()  argument
1400 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_disable_bmsr1()
1401 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_disable_bmsr1()
1402 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_bmsr1()
1407 bnx2_test_and_enable_2g5(struct bnx2 *bp)  in bnx2_test_and_enable_2g5()  argument
1412 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_enable_2g5()
1415 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_test_and_enable_2g5()
1416 		bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_test_and_enable_2g5()
1418 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1419 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_enable_2g5()
1421 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_enable_2g5()
1424 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_enable_2g5()
1428 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1429 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_enable_2g5()
1436 bnx2_test_and_disable_2g5(struct bnx2 *bp)  in bnx2_test_and_disable_2g5()  argument
1441 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_disable_2g5()
1444 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1445 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_disable_2g5()
1447 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_disable_2g5()
1450 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_disable_2g5()
1454 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1455 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_disable_2g5()
1462 bnx2_enable_forced_2g5(struct bnx2 *bp)  in bnx2_enable_forced_2g5()  argument
1467 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_enable_forced_2g5()
1470 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_enable_forced_2g5()
1473 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1475 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_enable_forced_2g5()
1479 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_enable_forced_2g5()
1482 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1484 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1486 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_enable_forced_2g5()
1487 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1497 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_enable_forced_2g5()
1499 		if (bp->req_duplex == DUPLEX_FULL)  in bnx2_enable_forced_2g5()
1502 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_enable_forced_2g5()
1506 bnx2_disable_forced_2g5(struct bnx2 *bp)  in bnx2_disable_forced_2g5()  argument
1511 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_disable_forced_2g5()
1514 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_disable_forced_2g5()
1517 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1519 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_disable_forced_2g5()
1521 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_disable_forced_2g5()
1524 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1526 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1528 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_disable_forced_2g5()
1529 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1539 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_disable_forced_2g5()
1541 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_disable_forced_2g5()
1545 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)  in bnx2_5706s_force_link_dn()  argument
1549 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);  in bnx2_5706s_force_link_dn()
1550 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_5706s_force_link_dn()
1552 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);  in bnx2_5706s_force_link_dn()
1554 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);  in bnx2_5706s_force_link_dn()
1558 bnx2_set_link(struct bnx2 *bp)  in bnx2_set_link()  argument
1563 	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {  in bnx2_set_link()
1564 		bp->link_up = 1;  in bnx2_set_link()
1568 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_set_link()
1571 	link_up = bp->link_up;  in bnx2_set_link()
1573 	bnx2_enable_bmsr1(bp);  in bnx2_set_link()
1574 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1575 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1576 	bnx2_disable_bmsr1(bp);  in bnx2_set_link()
1578 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1579 	    (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {  in bnx2_set_link()
1582 		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {  in bnx2_set_link()
1583 			bnx2_5706s_force_link_dn(bp, 0);  in bnx2_set_link()
1584 			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_set_link()
1586 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
1588 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_set_link()
1589 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1590 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1600 		bp->link_up = 1;  in bnx2_set_link()
1602 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_link()
1603 			if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_set_link()
1604 				bnx2_5706s_linkup(bp);  in bnx2_set_link()
1605 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_set_link()
1606 				bnx2_5708s_linkup(bp);  in bnx2_set_link()
1607 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_set_link()
1608 				bnx2_5709s_linkup(bp);  in bnx2_set_link()
1611 			bnx2_copper_linkup(bp);  in bnx2_set_link()
1613 		bnx2_resolve_flow_ctrl(bp);  in bnx2_set_link()
1616 		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1617 		    (bp->autoneg & AUTONEG_SPEED))  in bnx2_set_link()
1618 			bnx2_disable_forced_2g5(bp);  in bnx2_set_link()
1620 		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {  in bnx2_set_link()
1623 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_set_link()
1625 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_set_link()
1627 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_set_link()
1629 		bp->link_up = 0;  in bnx2_set_link()
1632 	if (bp->link_up != link_up) {  in bnx2_set_link()
1633 		bnx2_report_link(bp);  in bnx2_set_link()
1636 	bnx2_set_mac_link(bp);  in bnx2_set_link()
1642 bnx2_reset_phy(struct bnx2 *bp)  in bnx2_reset_phy()  argument
1647         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);  in bnx2_reset_phy()
1653 		bnx2_read_phy(bp, bp->mii_bmcr, &reg);  in bnx2_reset_phy()
1666 bnx2_phy_get_pause_adv(struct bnx2 *bp)  in bnx2_phy_get_pause_adv()  argument
1670 	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==  in bnx2_phy_get_pause_adv()
1673 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1680 	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {  in bnx2_phy_get_pause_adv()
1681 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1688 	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {  in bnx2_phy_get_pause_adv()
1689 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1702 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_remote_phy()  argument
1703 __releases(&bp->phy_lock)  in bnx2_setup_remote_phy()
1704 __acquires(&bp->phy_lock)  in bnx2_setup_remote_phy()
1708 	pause_adv = bnx2_phy_get_pause_adv(bp);  in bnx2_setup_remote_phy()
1710 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_remote_phy()
1712 		if (bp->advertising & ADVERTISED_10baseT_Half)  in bnx2_setup_remote_phy()
1714 		if (bp->advertising & ADVERTISED_10baseT_Full)  in bnx2_setup_remote_phy()
1716 		if (bp->advertising & ADVERTISED_100baseT_Half)  in bnx2_setup_remote_phy()
1718 		if (bp->advertising & ADVERTISED_100baseT_Full)  in bnx2_setup_remote_phy()
1720 		if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_remote_phy()
1722 		if (bp->advertising & ADVERTISED_2500baseX_Full)  in bnx2_setup_remote_phy()
1725 		if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_remote_phy()
1727 		else if (bp->req_line_speed == SPEED_1000)  in bnx2_setup_remote_phy()
1729 		else if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_remote_phy()
1730 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1734 		} else if (bp->req_line_speed == SPEED_10) {  in bnx2_setup_remote_phy()
1735 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1751 	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);  in bnx2_setup_remote_phy()
1753 	spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1754 	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);  in bnx2_setup_remote_phy()
1755 	spin_lock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1761 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_serdes_phy()  argument
1762 __releases(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1763 __acquires(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1768 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_setup_serdes_phy()
1769 		return bnx2_setup_remote_phy(bp, port);  in bnx2_setup_serdes_phy()
1771 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_setup_serdes_phy()
1775 		if (bp->req_line_speed == SPEED_2500) {  in bnx2_setup_serdes_phy()
1776 			if (!bnx2_test_and_enable_2g5(bp))  in bnx2_setup_serdes_phy()
1778 		} else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1779 			if (bnx2_test_and_disable_2g5(bp))  in bnx2_setup_serdes_phy()
1782 		bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1785 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1789 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_serdes_phy()
1790 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1791 				bnx2_enable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1792 			else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1793 				bnx2_disable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1797 		} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_setup_serdes_phy()
1798 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1804 		if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_serdes_phy()
1814 			if (bp->link_up) {  in bnx2_setup_serdes_phy()
1815 				bnx2_write_phy(bp, bp->mii_adv, adv &  in bnx2_setup_serdes_phy()
1818 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |  in bnx2_setup_serdes_phy()
1821 				bp->link_up = 0;  in bnx2_setup_serdes_phy()
1822 				netif_carrier_off(bp->dev);  in bnx2_setup_serdes_phy()
1823 				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1824 				bnx2_report_link(bp);  in bnx2_setup_serdes_phy()
1826 			bnx2_write_phy(bp, bp->mii_adv, adv);  in bnx2_setup_serdes_phy()
1827 			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1829 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1830 			bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1835 	bnx2_test_and_enable_2g5(bp);  in bnx2_setup_serdes_phy()
1837 	if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_serdes_phy()
1840 	new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_serdes_phy()
1842 	bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1843 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1845 	bp->serdes_an_pending = 0;  in bnx2_setup_serdes_phy()
1848 		if (bp->link_up) {  in bnx2_setup_serdes_phy()
1849 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_serdes_phy()
1850 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1852 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1855 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_serdes_phy()
1856 		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |  in bnx2_setup_serdes_phy()
1866 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_setup_serdes_phy()
1867 		bp->serdes_an_pending = 1;  in bnx2_setup_serdes_phy()
1868 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_setup_serdes_phy()
1870 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1871 		bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1878 	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1893 bnx2_set_default_remote_link(struct bnx2 *bp)  in bnx2_set_default_remote_link()  argument
1897 	if (bp->phy_port == PORT_TP)  in bnx2_set_default_remote_link()
1898 		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);  in bnx2_set_default_remote_link()
1900 		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);  in bnx2_set_default_remote_link()
1903 		bp->req_line_speed = 0;  in bnx2_set_default_remote_link()
1904 		bp->autoneg |= AUTONEG_SPEED;  in bnx2_set_default_remote_link()
1905 		bp->advertising = ADVERTISED_Autoneg;  in bnx2_set_default_remote_link()
1907 			bp->advertising |= ADVERTISED_10baseT_Half;  in bnx2_set_default_remote_link()
1909 			bp->advertising |= ADVERTISED_10baseT_Full;  in bnx2_set_default_remote_link()
1911 			bp->advertising |= ADVERTISED_100baseT_Half;  in bnx2_set_default_remote_link()
1913 			bp->advertising |= ADVERTISED_100baseT_Full;  in bnx2_set_default_remote_link()
1915 			bp->advertising |= ADVERTISED_1000baseT_Full;  in bnx2_set_default_remote_link()
1917 			bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_set_default_remote_link()
1919 		bp->autoneg = 0;  in bnx2_set_default_remote_link()
1920 		bp->advertising = 0;  in bnx2_set_default_remote_link()
1921 		bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_remote_link()
1923 			bp->req_line_speed = SPEED_10;  in bnx2_set_default_remote_link()
1925 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1928 			bp->req_line_speed = SPEED_100;  in bnx2_set_default_remote_link()
1930 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1933 			bp->req_line_speed = SPEED_1000;  in bnx2_set_default_remote_link()
1935 			bp->req_line_speed = SPEED_2500;  in bnx2_set_default_remote_link()
1940 bnx2_set_default_link(struct bnx2 *bp)  in bnx2_set_default_link()  argument
1942 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_set_default_link()
1943 		bnx2_set_default_remote_link(bp);  in bnx2_set_default_link()
1947 	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;  in bnx2_set_default_link()
1948 	bp->req_line_speed = 0;  in bnx2_set_default_link()
1949 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_default_link()
1952 		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1954 		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);  in bnx2_set_default_link()
1957 			bp->autoneg = 0;  in bnx2_set_default_link()
1958 			bp->req_line_speed = bp->line_speed = SPEED_1000;  in bnx2_set_default_link()
1959 			bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_link()
1962 		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1966 bnx2_send_heart_beat(struct bnx2 *bp)  in bnx2_send_heart_beat()  argument
1971 	spin_lock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1972 	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);  in bnx2_send_heart_beat()
1973 	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;  in bnx2_send_heart_beat()
1974 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1975 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
1976 	spin_unlock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1980 bnx2_remote_phy_event(struct bnx2 *bp)  in bnx2_remote_phy_event()  argument
1983 	u8 link_up = bp->link_up;  in bnx2_remote_phy_event()
1986 	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_remote_phy_event()
1989 		bnx2_send_heart_beat(bp);  in bnx2_remote_phy_event()
1994 		bp->link_up = 0;  in bnx2_remote_phy_event()
1998 		bp->link_up = 1;  in bnx2_remote_phy_event()
2000 		bp->duplex = DUPLEX_FULL;  in bnx2_remote_phy_event()
2003 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2006 				bp->line_speed = SPEED_10;  in bnx2_remote_phy_event()
2009 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2013 				bp->line_speed = SPEED_100;  in bnx2_remote_phy_event()
2016 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2019 				bp->line_speed = SPEED_1000;  in bnx2_remote_phy_event()
2022 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2025 				bp->line_speed = SPEED_2500;  in bnx2_remote_phy_event()
2028 				bp->line_speed = 0;  in bnx2_remote_phy_event()
2032 		bp->flow_ctrl = 0;  in bnx2_remote_phy_event()
2033 		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_remote_phy_event()
2035 			if (bp->duplex == DUPLEX_FULL)  in bnx2_remote_phy_event()
2036 				bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_remote_phy_event()
2039 				bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_remote_phy_event()
2041 				bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_remote_phy_event()
2044 		old_port = bp->phy_port;  in bnx2_remote_phy_event()
2046 			bp->phy_port = PORT_FIBRE;  in bnx2_remote_phy_event()
2048 			bp->phy_port = PORT_TP;  in bnx2_remote_phy_event()
2050 		if (old_port != bp->phy_port)  in bnx2_remote_phy_event()
2051 			bnx2_set_default_link(bp);  in bnx2_remote_phy_event()
2054 	if (bp->link_up != link_up)  in bnx2_remote_phy_event()
2055 		bnx2_report_link(bp);  in bnx2_remote_phy_event()
2057 	bnx2_set_mac_link(bp);  in bnx2_remote_phy_event()
2061 bnx2_set_remote_link(struct bnx2 *bp)  in bnx2_set_remote_link()  argument
2065 	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);  in bnx2_set_remote_link()
2068 			bnx2_remote_phy_event(bp);  in bnx2_set_remote_link()
2072 			bnx2_send_heart_beat(bp);  in bnx2_set_remote_link()
2079 bnx2_setup_copper_phy(struct bnx2 *bp)  in bnx2_setup_copper_phy()  argument
2080 __releases(&bp->phy_lock)  in bnx2_setup_copper_phy()
2081 __acquires(&bp->phy_lock)  in bnx2_setup_copper_phy()
2086 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_copper_phy()
2088 	bnx2_read_phy(bp, bp->mii_adv, &adv_reg);  in bnx2_setup_copper_phy()
2092 	new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);  in bnx2_setup_copper_phy()
2094 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_copper_phy()
2098 		new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_copper_phy()
2100 		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);  in bnx2_setup_copper_phy()
2103 		new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);  in bnx2_setup_copper_phy()
2108 			bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2109 			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);  in bnx2_setup_copper_phy()
2110 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |  in bnx2_setup_copper_phy()
2113 		else if (bp->link_up) {  in bnx2_setup_copper_phy()
2117 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2118 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2125 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2128 	if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_copper_phy()
2131 	if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_copper_phy()
2137 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2138 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2142 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_copper_phy()
2143 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2145 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2147 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2148 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2151 		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_copper_phy()
2158 			bp->line_speed = bp->req_line_speed;  in bnx2_setup_copper_phy()
2159 			bp->duplex = bp->req_duplex;  in bnx2_setup_copper_phy()
2160 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2161 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2164 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2165 		bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2171 bnx2_setup_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_phy()  argument
2172 __releases(&bp->phy_lock)  in bnx2_setup_phy()
2173 __acquires(&bp->phy_lock)  in bnx2_setup_phy()
2175 	if (bp->loopback == MAC_LOOPBACK)  in bnx2_setup_phy()
2178 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_setup_phy()
2179 		return bnx2_setup_serdes_phy(bp, port);  in bnx2_setup_phy()
2182 		return bnx2_setup_copper_phy(bp);  in bnx2_setup_phy()
2187 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5709s_phy()  argument
2191 	bp->mii_bmcr = MII_BMCR + 0x10;  in bnx2_init_5709s_phy()
2192 	bp->mii_bmsr = MII_BMSR + 0x10;  in bnx2_init_5709s_phy()
2193 	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;  in bnx2_init_5709s_phy()
2194 	bp->mii_adv = MII_ADVERTISE + 0x10;  in bnx2_init_5709s_phy()
2195 	bp->mii_lpa = MII_LPA + 0x10;  in bnx2_init_5709s_phy()
2196 	bp->mii_up1 = MII_BNX2_OVER1G_UP1;  in bnx2_init_5709s_phy()
2198 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);  in bnx2_init_5709s_phy()
2199 	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);  in bnx2_init_5709s_phy()
2201 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2203 		bnx2_reset_phy(bp);  in bnx2_init_5709s_phy()
2205 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);  in bnx2_init_5709s_phy()
2207 	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);  in bnx2_init_5709s_phy()
2210 	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);  in bnx2_init_5709s_phy()
2212 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_init_5709s_phy()
2213 	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);  in bnx2_init_5709s_phy()
2214 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_init_5709s_phy()
2218 	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);  in bnx2_init_5709s_phy()
2220 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);  in bnx2_init_5709s_phy()
2221 	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);  in bnx2_init_5709s_phy()
2223 	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);  in bnx2_init_5709s_phy()
2225 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);  in bnx2_init_5709s_phy()
2229 	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);  in bnx2_init_5709s_phy()
2231 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2237 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5708s_phy()  argument
2242 		bnx2_reset_phy(bp);  in bnx2_init_5708s_phy()
2244 	bp->mii_up1 = BCM5708S_UP1;  in bnx2_init_5708s_phy()
2246 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);  in bnx2_init_5708s_phy()
2247 	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);  in bnx2_init_5708s_phy()
2248 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2250 	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);  in bnx2_init_5708s_phy()
2252 	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);  in bnx2_init_5708s_phy()
2254 	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);  in bnx2_init_5708s_phy()
2256 	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);  in bnx2_init_5708s_phy()
2258 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {  in bnx2_init_5708s_phy()
2259 		bnx2_read_phy(bp, BCM5708S_UP1, &val);  in bnx2_init_5708s_phy()
2261 		bnx2_write_phy(bp, BCM5708S_UP1, val);  in bnx2_init_5708s_phy()
2264 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_5708s_phy()
2265 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_5708s_phy()
2266 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {  in bnx2_init_5708s_phy()
2268 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2270 		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);  in bnx2_init_5708s_phy()
2272 		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);  in bnx2_init_5708s_phy()
2273 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2276 	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &  in bnx2_init_5708s_phy()
2282 		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_5708s_phy()
2284 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2286 			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);  in bnx2_init_5708s_phy()
2287 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2295 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5706s_phy()  argument
2298 		bnx2_reset_phy(bp);  in bnx2_init_5706s_phy()
2300 	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_init_5706s_phy()
2302 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_5706s_phy()
2303 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2305 	if (bp->dev->mtu > ETH_DATA_LEN) {  in bnx2_init_5706s_phy()
2309 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2310 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2311 		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);  in bnx2_init_5706s_phy()
2313 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2314 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2315 		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);  in bnx2_init_5706s_phy()
2320 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2321 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2322 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_5706s_phy()
2324 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2325 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2326 		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);  in bnx2_init_5706s_phy()
2333 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_copper_phy()  argument
2338 		bnx2_reset_phy(bp);  in bnx2_init_copper_phy()
2340 	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {  in bnx2_init_copper_phy()
2341 		bnx2_write_phy(bp, 0x18, 0x0c00);  in bnx2_init_copper_phy()
2342 		bnx2_write_phy(bp, 0x17, 0x000a);  in bnx2_init_copper_phy()
2343 		bnx2_write_phy(bp, 0x15, 0x310b);  in bnx2_init_copper_phy()
2344 		bnx2_write_phy(bp, 0x17, 0x201f);  in bnx2_init_copper_phy()
2345 		bnx2_write_phy(bp, 0x15, 0x9506);  in bnx2_init_copper_phy()
2346 		bnx2_write_phy(bp, 0x17, 0x401f);  in bnx2_init_copper_phy()
2347 		bnx2_write_phy(bp, 0x15, 0x14e2);  in bnx2_init_copper_phy()
2348 		bnx2_write_phy(bp, 0x18, 0x0400);  in bnx2_init_copper_phy()
2351 	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {  in bnx2_init_copper_phy()
2352 		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,  in bnx2_init_copper_phy()
2354 		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_init_copper_phy()
2356 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);  in bnx2_init_copper_phy()
2359 	if (bp->dev->mtu > ETH_DATA_LEN) {  in bnx2_init_copper_phy()
2361 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2362 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2363 		bnx2_write_phy(bp, 0x18, val | 0x4000);  in bnx2_init_copper_phy()
2365 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2366 		bnx2_write_phy(bp, 0x10, val | 0x1);  in bnx2_init_copper_phy()
2369 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2370 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2371 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_copper_phy()
2373 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2374 		bnx2_write_phy(bp, 0x10, val & ~0x1);  in bnx2_init_copper_phy()
2378 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);  in bnx2_init_copper_phy()
2379 	bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);  in bnx2_init_copper_phy()
2383 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_copper_phy()
2386 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);  in bnx2_init_copper_phy()
2392 bnx2_init_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_phy()  argument
2393 __releases(&bp->phy_lock)  in bnx2_init_phy()
2394 __acquires(&bp->phy_lock)  in bnx2_init_phy()
2399 	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;  in bnx2_init_phy()
2400 	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;  in bnx2_init_phy()
2402 	bp->mii_bmcr = MII_BMCR;  in bnx2_init_phy()
2403 	bp->mii_bmsr = MII_BMSR;  in bnx2_init_phy()
2404 	bp->mii_bmsr1 = MII_BMSR;  in bnx2_init_phy()
2405 	bp->mii_adv = MII_ADVERTISE;  in bnx2_init_phy()
2406 	bp->mii_lpa = MII_LPA;  in bnx2_init_phy()
2408 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2410 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_phy()
2413 	bnx2_read_phy(bp, MII_PHYSID1, &val);  in bnx2_init_phy()
2414 	bp->phy_id = val << 16;  in bnx2_init_phy()
2415 	bnx2_read_phy(bp, MII_PHYSID2, &val);  in bnx2_init_phy()
2416 	bp->phy_id |= val & 0xffff;  in bnx2_init_phy()
2418 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_phy()
2419 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_phy()
2420 			rc = bnx2_init_5706s_phy(bp, reset_phy);  in bnx2_init_phy()
2421 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_phy()
2422 			rc = bnx2_init_5708s_phy(bp, reset_phy);  in bnx2_init_phy()
2423 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_phy()
2424 			rc = bnx2_init_5709s_phy(bp, reset_phy);  in bnx2_init_phy()
2427 		rc = bnx2_init_copper_phy(bp, reset_phy);  in bnx2_init_phy()
2432 		rc = bnx2_setup_phy(bp, bp->phy_port);  in bnx2_init_phy()
2438 bnx2_set_mac_loopback(struct bnx2 *bp)  in bnx2_set_mac_loopback()  argument
2442 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2445 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2446 	bp->link_up = 1;  in bnx2_set_mac_loopback()
2453 bnx2_set_phy_loopback(struct bnx2 *bp)  in bnx2_set_phy_loopback()  argument
2458 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2459 	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |  in bnx2_set_phy_loopback()
2461 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2466 		if (bnx2_test_link(bp) == 0)  in bnx2_set_phy_loopback()
2471 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2477 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2478 	bp->link_up = 1;  in bnx2_set_phy_loopback()
2483 bnx2_dump_mcp_state(struct bnx2 *bp)  in bnx2_dump_mcp_state()  argument
2485 	struct net_device *dev = bp->dev;  in bnx2_dump_mcp_state()
2489 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_dump_mcp_state()
2497 		   bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));  in bnx2_dump_mcp_state()
2499 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),  in bnx2_dump_mcp_state()
2500 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),  in bnx2_dump_mcp_state()
2501 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));  in bnx2_dump_mcp_state()
2503 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2504 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2505 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));  in bnx2_dump_mcp_state()
2508 		   bnx2_shmem_rd(bp, BNX2_DRV_MB),  in bnx2_dump_mcp_state()
2509 		   bnx2_shmem_rd(bp, BNX2_FW_MB),  in bnx2_dump_mcp_state()
2510 		   bnx2_shmem_rd(bp, BNX2_LINK_STATUS));  in bnx2_dump_mcp_state()
2511 	pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));  in bnx2_dump_mcp_state()
2513 		   bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),  in bnx2_dump_mcp_state()
2514 		   bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));  in bnx2_dump_mcp_state()
2516 		bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));  in bnx2_dump_mcp_state()
2517 	DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);  in bnx2_dump_mcp_state()
2518 	DP_SHMEM_LINE(bp, 0x3cc);  in bnx2_dump_mcp_state()
2519 	DP_SHMEM_LINE(bp, 0x3dc);  in bnx2_dump_mcp_state()
2520 	DP_SHMEM_LINE(bp, 0x3ec);  in bnx2_dump_mcp_state()
2521 	netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));  in bnx2_dump_mcp_state()
2526 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)  in bnx2_fw_sync()  argument
2531 	bp->fw_wr_seq++;  in bnx2_fw_sync()
2532 	msg_data |= bp->fw_wr_seq;  in bnx2_fw_sync()
2533 	bp->fw_last_msg = msg_data;  in bnx2_fw_sync()
2535 	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2544 		val = bnx2_shmem_rd(bp, BNX2_FW_MB);  in bnx2_fw_sync()
2557 		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2560 			bnx2_dump_mcp_state(bp);  in bnx2_fw_sync()
2573 bnx2_init_5709_context(struct bnx2 *bp)  in bnx2_init_5709_context()  argument
2580 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2582 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2590 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_init_5709_context()
2593 		if (bp->ctx_blk[i])  in bnx2_init_5709_context()
2594 			memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);  in bnx2_init_5709_context()
2598 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2599 			(bp->ctx_blk_mapping[i] & 0xffffffff) |  in bnx2_init_5709_context()
2601 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2602 			(u64) bp->ctx_blk_mapping[i] >> 32);  in bnx2_init_5709_context()
2603 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2607 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
2621 bnx2_init_context(struct bnx2 *bp)  in bnx2_init_context()  argument
2632 		if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_context()
2653 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2654 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2658 				bnx2_ctx_wr(bp, vcid_addr, offset, 0);  in bnx2_init_context()
2664 bnx2_alloc_bad_rbuf(struct bnx2 *bp)  in bnx2_alloc_bad_rbuf()  argument
2674 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2680 	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2682 		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,  in bnx2_alloc_bad_rbuf()
2685 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);  in bnx2_alloc_bad_rbuf()
2695 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2706 		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);  in bnx2_alloc_bad_rbuf()
2713 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)  in bnx2_set_mac_addr()  argument
2719 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2724 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2728 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_page()  argument
2738 	mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,  in bnx2_alloc_rx_page()
2740 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_page()
2753 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)  in bnx2_free_rx_page()  argument
2761 	dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),  in bnx2_free_rx_page()
2769 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_data()  argument
2777 	data = kmalloc(bp->rx_buf_size, gfp);  in bnx2_alloc_rx_data()
2781 	mapping = dma_map_single(&bp->pdev->dev,  in bnx2_alloc_rx_data()
2783 				 bp->rx_buf_use_size,  in bnx2_alloc_rx_data()
2785 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_data()
2796 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_alloc_rx_data()
2802 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)  in bnx2_phy_event_is_set()  argument
2812 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2814 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
2822 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_phy_int()  argument
2824 	spin_lock(&bp->phy_lock);  in bnx2_phy_int()
2826 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))  in bnx2_phy_int()
2827 		bnx2_set_link(bp);  in bnx2_phy_int()
2828 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))  in bnx2_phy_int()
2829 		bnx2_set_remote_link(bp);  in bnx2_phy_int()
2831 	spin_unlock(&bp->phy_lock);  in bnx2_phy_int()
2848 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_tx_int()  argument
2856 	index = (bnapi - bp->bnx2_napi);  in bnx2_tx_int()
2857 	txq = netdev_get_tx_queue(bp->dev, index);  in bnx2_tx_int()
2889 		dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_tx_int()
2901 			dma_unmap_page(&bp->pdev->dev,  in bnx2_tx_int()
2931 		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {  in bnx2_tx_int()
2934 		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))  in bnx2_tx_int()
2943 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_skb_pages()  argument
3001 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_data()  argument
3010 	dma_sync_single_for_device(&bp->pdev->dev,  in bnx2_reuse_rx_data()
3014 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_reuse_rx_data()
3031 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,  in bnx2_rx_skb()  argument
3039 	err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);  in bnx2_rx_skb()
3041 		bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);  in bnx2_rx_skb()
3047 			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_skb()
3052 	dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,  in bnx2_rx_skb()
3082 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,  in bnx2_rx_skb()
3107 			err = bnx2_alloc_rx_page(bp, rxr,  in bnx2_rx_skb()
3113 				bnx2_reuse_rx_skb_pages(bp, rxr, skb,  in bnx2_rx_skb()
3118 			dma_unmap_page(&bp->pdev->dev, mapping_old,  in bnx2_rx_skb()
3148 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_rx_int()  argument
3187 		dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,  in bnx2_rx_int()
3202 		} else if (len > bp->rx_jumbo_thresh) {  in bnx2_rx_int()
3203 			hdr_len = bp->rx_jumbo_thresh;  in bnx2_rx_int()
3213 			bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3220 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_int()
3227 		if (len <= bp->rx_copy_thresh) {  in bnx2_rx_int()
3228 			skb = netdev_alloc_skb(bp->dev, len + 6);  in bnx2_rx_int()
3230 				bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3242 			bnx2_reuse_rx_data(bp, rxr, data,  in bnx2_rx_int()
3246 			skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,  in bnx2_rx_int()
3252 		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))  in bnx2_rx_int()
3255 		skb->protocol = eth_type_trans(skb, bp->dev);  in bnx2_rx_int()
3257 		if (len > (bp->dev->mtu + ETH_HLEN) &&  in bnx2_rx_int()
3267 		if ((bp->dev->features & NETIF_F_RXCSUM) &&  in bnx2_rx_int()
3275 		if ((bp->dev->features & NETIF_F_RXHASH) &&  in bnx2_rx_int()
3281 		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);  in bnx2_rx_int()
3302 		BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_rx_int()
3304 	BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);  in bnx2_rx_int()
3306 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3321 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi()  local
3324 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3329 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi()
3341 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi_1shot()  local
3346 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi_1shot()
3358 	struct bnx2 *bp = bnapi->bp;  in bnx2_interrupt()  local
3368 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3372 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3379 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3382 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_interrupt()
3429 bnx2_chk_missed_msi(struct bnx2 *bp)  in bnx2_chk_missed_msi()  argument
3431 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_chk_missed_msi()
3435 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3439 		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {  in bnx2_chk_missed_msi()
3440 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3442 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3443 			bnx2_msi(bp->irq_tbl[0].vector, bnapi);  in bnx2_chk_missed_msi()
3447 	bp->idle_chk_status_idx = bnapi->last_status_idx;  in bnx2_chk_missed_msi()
3451 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_cnic()  argument
3459 	c_ops = rcu_dereference(bp->cnic_ops);  in bnx2_poll_cnic()
3461 		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,  in bnx2_poll_cnic()
3467 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_link()  argument
3476 		bnx2_phy_int(bp, bnapi);  in bnx2_poll_link()
3481 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3482 			bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_poll_link()
3483 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3487 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,  in bnx2_poll_work()  argument
3494 		bnx2_tx_int(bp, bnapi, 0);  in bnx2_poll_work()
3497 		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);  in bnx2_poll_work()
3505 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll_msix()  local
3510 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll_msix()
3520 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3532 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll()  local
3537 		bnx2_poll_link(bp, bnapi);  in bnx2_poll()
3539 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll()
3542 		bnx2_poll_cnic(bp, bnapi);  in bnx2_poll()
3557 			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {  in bnx2_poll()
3558 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3563 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3568 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3584 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_rx_mode()  local
3592 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3594 	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |  in bnx2_set_rx_mode()
3598 	     (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_set_rx_mode()
3608 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3631 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3646 			bnx2_set_mac_addr(bp, ha->addr,  in bnx2_set_rx_mode()
3655 	if (rx_mode != bp->rx_mode) {  in bnx2_set_rx_mode()
3656 		bp->rx_mode = rx_mode;  in bnx2_set_rx_mode()
3657 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3660 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3661 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3662 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3664 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3694 static void bnx2_release_firmware(struct bnx2 *bp)  in bnx2_release_firmware()  argument
3696 	if (bp->rv2p_firmware) {  in bnx2_release_firmware()
3697 		release_firmware(bp->mips_firmware);  in bnx2_release_firmware()
3698 		release_firmware(bp->rv2p_firmware);  in bnx2_release_firmware()
3699 		bp->rv2p_firmware = NULL;  in bnx2_release_firmware()
3703 static int bnx2_request_uncached_firmware(struct bnx2 *bp)  in bnx2_request_uncached_firmware()  argument
3710 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_request_uncached_firmware()
3712 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||  in bnx2_request_uncached_firmware()
3713 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))  in bnx2_request_uncached_firmware()
3722 	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3728 	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3733 	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_request_uncached_firmware()
3734 	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_request_uncached_firmware()
3735 	if (bp->mips_firmware->size < sizeof(*mips_fw) ||  in bnx2_request_uncached_firmware()
3736 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||  in bnx2_request_uncached_firmware()
3737 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||  in bnx2_request_uncached_firmware()
3738 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||  in bnx2_request_uncached_firmware()
3739 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||  in bnx2_request_uncached_firmware()
3740 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {  in bnx2_request_uncached_firmware()
3745 	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||  in bnx2_request_uncached_firmware()
3746 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||  in bnx2_request_uncached_firmware()
3747 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {  in bnx2_request_uncached_firmware()
3756 	release_firmware(bp->rv2p_firmware);  in bnx2_request_uncached_firmware()
3757 	bp->rv2p_firmware = NULL;  in bnx2_request_uncached_firmware()
3759 	release_firmware(bp->mips_firmware);  in bnx2_request_uncached_firmware()
3763 static int bnx2_request_firmware(struct bnx2 *bp)  in bnx2_request_firmware()  argument
3765 	return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);  in bnx2_request_firmware()
3781 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,  in load_rv2p_fw()  argument
3792 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3803 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3805 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3809 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3812 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3819 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3822 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3825 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3831 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3834 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3841 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,  in load_cpu_fw()  argument
3850 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3852 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3853 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3859 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3866 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3873 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3880 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3887 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3894 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3898 	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);  in load_cpu_fw()
3901 	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);  in load_cpu_fw()
3904 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3906 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3907 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3913 bnx2_init_cpus(struct bnx2 *bp)  in bnx2_init_cpus()  argument
3916 		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_init_cpus()
3918 		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_init_cpus()
3922 	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);  in bnx2_init_cpus()
3923 	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);  in bnx2_init_cpus()
3926 	rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);  in bnx2_init_cpus()
3931 	rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);  in bnx2_init_cpus()
3936 	rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);  in bnx2_init_cpus()
3941 	rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);  in bnx2_init_cpus()
3946 	rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);  in bnx2_init_cpus()
3953 bnx2_setup_wol(struct bnx2 *bp)  in bnx2_setup_wol()  argument
3958 	if (bp->wol) {  in bnx2_setup_wol()
3962 		autoneg = bp->autoneg;  in bnx2_setup_wol()
3963 		advertising = bp->advertising;  in bnx2_setup_wol()
3965 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3966 			bp->autoneg = AUTONEG_SPEED;  in bnx2_setup_wol()
3967 			bp->advertising = ADVERTISED_10baseT_Half |  in bnx2_setup_wol()
3974 		spin_lock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3975 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_setup_wol()
3976 		spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3978 		bp->autoneg = autoneg;  in bnx2_setup_wol()
3979 		bp->advertising = advertising;  in bnx2_setup_wol()
3981 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_setup_wol()
3983 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
3990 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3994 			if (bp->line_speed == SPEED_2500)  in bnx2_setup_wol()
3998 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
4002 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
4005 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
4008 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
4009 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
4010 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
4013 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
4018 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
4020 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4027 	if (!(bp->flags & BNX2_FLAG_NO_WOL)) {  in bnx2_setup_wol()
4031 		if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {  in bnx2_setup_wol()
4032 			bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4038 		val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_setup_wol()
4039 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,  in bnx2_setup_wol()
4041 		bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4042 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);  in bnx2_setup_wol()
4048 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)  in bnx2_set_power_state()  argument
4054 		pci_enable_wake(bp->pdev, PCI_D0, false);  in bnx2_set_power_state()
4055 		pci_set_power_state(bp->pdev, PCI_D0);  in bnx2_set_power_state()
4057 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4060 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4062 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4064 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4068 		bnx2_setup_wol(bp);  in bnx2_set_power_state()
4069 		pci_wake_from_d3(bp->pdev, bp->wol);  in bnx2_set_power_state()
4070 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_set_power_state()
4071 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {  in bnx2_set_power_state()
4073 			if (bp->wol)  in bnx2_set_power_state()
4074 				pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4078 		if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_set_power_state()
4085 			val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_set_power_state()
4088 			bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);  in bnx2_set_power_state()
4090 		pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4104 bnx2_acquire_nvram_lock(struct bnx2 *bp)  in bnx2_acquire_nvram_lock()  argument
4110 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4112 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4126 bnx2_release_nvram_lock(struct bnx2 *bp)  in bnx2_release_nvram_lock()  argument
4132 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4135 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4150 bnx2_enable_nvram_write(struct bnx2 *bp)  in bnx2_enable_nvram_write()  argument
4154 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4155 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4157 	if (bp->flash_info->flags & BNX2_NV_WREN) {  in bnx2_enable_nvram_write()
4160 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4161 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4167 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4179 bnx2_disable_nvram_write(struct bnx2 *bp)  in bnx2_disable_nvram_write()  argument
4183 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4184 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4189 bnx2_enable_nvram_access(struct bnx2 *bp)  in bnx2_enable_nvram_access()  argument
4193 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4195 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4200 bnx2_disable_nvram_access(struct bnx2 *bp)  in bnx2_disable_nvram_access()  argument
4204 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4206 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4212 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)  in bnx2_nvram_erase_page()  argument
4217 	if (bp->flash_info->flags & BNX2_NV_BUFFERED)  in bnx2_nvram_erase_page()
4226 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4229 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4232 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4240 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4252 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)  in bnx2_nvram_read_dword()  argument
4261 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_read_dword()
4262 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_read_dword()
4263 			   bp->flash_info->page_bits) +  in bnx2_nvram_read_dword()
4264 			  (offset % bp->flash_info->page_size);  in bnx2_nvram_read_dword()
4268 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4271 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4274 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4282 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4284 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4297 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)  in bnx2_nvram_write_dword()  argument
4307 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_write_dword()
4308 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_write_dword()
4309 			  bp->flash_info->page_bits) +  in bnx2_nvram_write_dword()
4310 			 (offset % bp->flash_info->page_size);  in bnx2_nvram_write_dword()
4314 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4319 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4322 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4325 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4331 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4341 bnx2_init_nvram(struct bnx2 *bp)  in bnx2_init_nvram()  argument
4347 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_nvram()
4348 		bp->flash_info = &flash_5709;  in bnx2_init_nvram()
4353 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4364 				bp->flash_info = flash;  in bnx2_init_nvram()
4382 				bp->flash_info = flash;  in bnx2_init_nvram()
4385 				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_init_nvram()
4389 				bnx2_enable_nvram_access(bp);  in bnx2_init_nvram()
4392 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4393 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4394 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4395 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4398 				bnx2_disable_nvram_access(bp);  in bnx2_init_nvram()
4399 				bnx2_release_nvram_lock(bp);  in bnx2_init_nvram()
4407 		bp->flash_info = NULL;  in bnx2_init_nvram()
4413 	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);  in bnx2_init_nvram()
4416 		bp->flash_size = val;  in bnx2_init_nvram()
4418 		bp->flash_size = bp->flash_info->total_size;  in bnx2_init_nvram()
4424 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,  in bnx2_nvram_read()  argument
4434 	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_read()
4438 	bnx2_enable_nvram_access(bp);  in bnx2_nvram_read()
4462 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4487 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4500 		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);  in bnx2_nvram_read()
4508 			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);  in bnx2_nvram_read()
4520 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4526 	bnx2_disable_nvram_access(bp);  in bnx2_nvram_read()
4528 	bnx2_release_nvram_lock(bp);  in bnx2_nvram_read()
4534 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,  in bnx2_nvram_write()  argument
4552 		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))  in bnx2_nvram_write()
4559 		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))  in bnx2_nvram_write()
4577 	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4593 		page_start -= (page_start % bp->flash_info->page_size);  in bnx2_nvram_write()
4595 		page_end = page_start + bp->flash_info->page_size;  in bnx2_nvram_write()
4603 		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_write()
4607 		bnx2_enable_nvram_access(bp);  in bnx2_nvram_write()
4610 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4615 			for (j = 0; j < bp->flash_info->page_size; j += 4) {  in bnx2_nvram_write()
4616 				if (j == (bp->flash_info->page_size - 4)) {  in bnx2_nvram_write()
4619 				rc = bnx2_nvram_read_dword(bp,  in bnx2_nvram_write()
4632 		if ((rc = bnx2_enable_nvram_write(bp)) != 0)  in bnx2_nvram_write()
4638 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4640 			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)  in bnx2_nvram_write()
4644 			bnx2_enable_nvram_write(bp);  in bnx2_nvram_write()
4649 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4662 				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&  in bnx2_nvram_write()
4667 			rc = bnx2_nvram_write_dword(bp, addr, buf,  in bnx2_nvram_write()
4679 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4686 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4697 		bnx2_disable_nvram_write(bp);  in bnx2_nvram_write()
4700 		bnx2_disable_nvram_access(bp);  in bnx2_nvram_write()
4701 		bnx2_release_nvram_lock(bp);  in bnx2_nvram_write()
4714 bnx2_init_fw_cap(struct bnx2 *bp)  in bnx2_init_fw_cap()  argument
4718 	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4719 	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4721 	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))  in bnx2_init_fw_cap()
4722 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4724 	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);  in bnx2_init_fw_cap()
4729 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4733 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_init_fw_cap()
4737 		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4739 		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_init_fw_cap()
4741 			bp->phy_port = PORT_FIBRE;  in bnx2_init_fw_cap()
4743 			bp->phy_port = PORT_TP;  in bnx2_init_fw_cap()
4749 	if (netif_running(bp->dev) && sig)  in bnx2_init_fw_cap()
4750 		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);  in bnx2_init_fw_cap()
4754 bnx2_setup_msix_tbl(struct bnx2 *bp)  in bnx2_setup_msix_tbl()  argument
4756 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4758 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4759 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4763 bnx2_wait_dma_complete(struct bnx2 *bp)  in bnx2_wait_dma_complete()  argument
4772 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_wait_dma_complete()
4773 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_wait_dma_complete()
4774 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_wait_dma_complete()
4779 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_wait_dma_complete()
4782 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_wait_dma_complete()
4784 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_wait_dma_complete()
4785 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_wait_dma_complete()
4789 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_wait_dma_complete()
4800 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_chip()  argument
4808 	bnx2_wait_dma_complete(bp);  in bnx2_reset_chip()
4811 	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);  in bnx2_reset_chip()
4815 	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,  in bnx2_reset_chip()
4820 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4822 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_reset_chip()
4823 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4824 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4830 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4838 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4844 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_reset_chip()
4845 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))  in bnx2_reset_chip()
4850 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4865 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4872 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);  in bnx2_reset_chip()
4876 	spin_lock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4877 	old_port = bp->phy_port;  in bnx2_reset_chip()
4878 	bnx2_init_fw_cap(bp);  in bnx2_reset_chip()
4879 	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&  in bnx2_reset_chip()
4880 	    old_port != bp->phy_port)  in bnx2_reset_chip()
4881 		bnx2_set_default_remote_link(bp);  in bnx2_reset_chip()
4882 	spin_unlock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4884 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_reset_chip()
4887 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4890 		rc = bnx2_alloc_bad_rbuf(bp);  in bnx2_reset_chip()
4893 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_reset_chip()
4894 		bnx2_setup_msix_tbl(bp);  in bnx2_reset_chip()
4896 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4904 bnx2_init_chip(struct bnx2 *bp)  in bnx2_init_chip()  argument
4910 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4923 	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))  in bnx2_init_chip()
4926 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&  in bnx2_init_chip()
4927 	    (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&  in bnx2_init_chip()
4928 	    !(bp->flags & BNX2_FLAG_PCIX))  in bnx2_init_chip()
4931 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4933 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_chip()
4934 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4936 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4939 	if (bp->flags & BNX2_FLAG_PCIX) {  in bnx2_init_chip()
4942 		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4944 		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4948 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4955 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4956 		rc = bnx2_init_5709_context(bp);  in bnx2_init_chip()
4960 		bnx2_init_context(bp);  in bnx2_init_chip()
4962 	if ((rc = bnx2_init_cpus(bp)) != 0)  in bnx2_init_chip()
4965 	bnx2_init_nvram(bp);  in bnx2_init_chip()
4967 	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_init_chip()
4969 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4972 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4974 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_chip()
4978 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4981 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4982 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4985 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4988 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
4991 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4993 	val = bp->mac_addr[0] +  in bnx2_init_chip()
4994 	      (bp->mac_addr[1] << 8) +  in bnx2_init_chip()
4995 	      (bp->mac_addr[2] << 16) +  in bnx2_init_chip()
4996 	      bp->mac_addr[3] +  in bnx2_init_chip()
4997 	      (bp->mac_addr[4] << 8) +  in bnx2_init_chip()
4998 	      (bp->mac_addr[5] << 16);  in bnx2_init_chip()
4999 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
5002 	mtu = bp->dev->mtu;  in bnx2_init_chip()
5006 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
5011 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));  in bnx2_init_chip()
5012 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));  in bnx2_init_chip()
5013 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));  in bnx2_init_chip()
5015 	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);  in bnx2_init_chip()
5017 		bp->bnx2_napi[i].last_status_idx = 0;  in bnx2_init_chip()
5019 	bp->idle_chk_status_idx = 0xffff;  in bnx2_init_chip()
5022 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
5024 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
5025 		(u64) bp->status_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5026 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
5028 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
5029 		(u64) bp->stats_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5030 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
5031 		(u64) bp->stats_blk_mapping >> 32);  in bnx2_init_chip()
5033 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5034 		(bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);  in bnx2_init_chip()
5036 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5037 		(bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);  in bnx2_init_chip()
5039 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5040 		(bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);  in bnx2_init_chip()
5042 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5044 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5046 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5047 		(bp->com_ticks_int << 16) | bp->com_ticks);  in bnx2_init_chip()
5049 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5050 		(bp->cmd_ticks_int << 16) | bp->cmd_ticks);  in bnx2_init_chip()
5052 	if (bp->flags & BNX2_FLAG_BROKEN_STATS)  in bnx2_init_chip()
5053 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5055 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5056 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5058 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)  in bnx2_init_chip()
5065 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_init_chip()
5066 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5072 	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)  in bnx2_init_chip()
5075 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5077 	if (bp->rx_ticks < 25)  in bnx2_init_chip()
5078 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);  in bnx2_init_chip()
5080 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);  in bnx2_init_chip()
5082 	for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_init_chip()
5086 		BNX2_WR(bp, base,  in bnx2_init_chip()
5091 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5092 			(bp->tx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5093 			 bp->tx_quick_cons_trip);  in bnx2_init_chip()
5095 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5096 			(bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5098 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5099 			(bp->rx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5100 			bp->rx_quick_cons_trip);  in bnx2_init_chip()
5102 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5103 			(bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5107 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5109 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5112 	bnx2_set_rx_mode(bp->dev);  in bnx2_init_chip()
5114 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
5115 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5117 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5119 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,  in bnx2_init_chip()
5122 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5123 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5127 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5133 bnx2_clear_ring_states(struct bnx2 *bp)  in bnx2_clear_ring_states()  argument
5141 		bnapi = &bp->bnx2_napi[i];  in bnx2_clear_ring_states()
5156 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)  in bnx2_init_tx_context()  argument
5161 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_tx_context()
5173 	bnx2_ctx_wr(bp, cid_addr, offset0, val);  in bnx2_init_tx_context()
5176 	bnx2_ctx_wr(bp, cid_addr, offset1, val);  in bnx2_init_tx_context()
5179 	bnx2_ctx_wr(bp, cid_addr, offset2, val);  in bnx2_init_tx_context()
5182 	bnx2_ctx_wr(bp, cid_addr, offset3, val);  in bnx2_init_tx_context()
5186 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_tx_ring()  argument
5193 	bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_tx_ring()
5201 	bp->tx_wake_thresh = bp->tx_ring_size / 2;  in bnx2_init_tx_ring()
5214 	bnx2_init_tx_context(bp, cid, txr);  in bnx2_init_tx_ring()
5242 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_rx_ring()  argument
5247 	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_rx_ring()
5258 			     bp->rx_buf_use_size, bp->rx_max_ring);  in bnx2_init_rx_ring()
5260 	bnx2_init_rx_context(bp, cid);  in bnx2_init_rx_ring()
5262 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_rx_ring()
5263 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5264 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5267 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);  in bnx2_init_rx_ring()
5268 	if (bp->rx_pg_ring_size) {  in bnx2_init_rx_ring()
5271 				     PAGE_SIZE, bp->rx_max_pg_ring);  in bnx2_init_rx_ring()
5272 		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;  in bnx2_init_rx_ring()
5273 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);  in bnx2_init_rx_ring()
5274 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,  in bnx2_init_rx_ring()
5278 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5281 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5283 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_rx_ring()
5284 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5288 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5291 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5294 	for (i = 0; i < bp->rx_pg_ring_size; i++) {  in bnx2_init_rx_ring()
5295 		if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5296 			netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",  in bnx2_init_rx_ring()
5297 				    ring_num, i, bp->rx_pg_ring_size);  in bnx2_init_rx_ring()
5306 	for (i = 0; i < bp->rx_ring_size; i++) {  in bnx2_init_rx_ring()
5307 		if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5308 			netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",  in bnx2_init_rx_ring()
5309 				    ring_num, i, bp->rx_ring_size);  in bnx2_init_rx_ring()
5321 	BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_init_rx_ring()
5322 	BNX2_WR16(bp, rxr->rx_bidx_addr, prod);  in bnx2_init_rx_ring()
5324 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5328 bnx2_init_all_rings(struct bnx2 *bp)  in bnx2_init_all_rings()  argument
5333 	bnx2_clear_ring_states(bp);  in bnx2_init_all_rings()
5335 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5336 	for (i = 0; i < bp->num_tx_rings; i++)  in bnx2_init_all_rings()
5337 		bnx2_init_tx_ring(bp, i);  in bnx2_init_all_rings()
5339 	if (bp->num_tx_rings > 1)  in bnx2_init_all_rings()
5340 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5343 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5344 	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);  in bnx2_init_all_rings()
5346 	for (i = 0; i < bp->num_rx_rings; i++)  in bnx2_init_all_rings()
5347 		bnx2_init_rx_ring(bp, i);  in bnx2_init_all_rings()
5349 	if (bp->num_rx_rings > 1) {  in bnx2_init_all_rings()
5355 			tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;  in bnx2_init_all_rings()
5357 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5358 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5369 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5394 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)  in bnx2_set_rx_ring_size()  argument
5399 	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;  in bnx2_set_rx_ring_size()
5404 	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;  in bnx2_set_rx_ring_size()
5405 	bp->rx_pg_ring_size = 0;  in bnx2_set_rx_ring_size()
5406 	bp->rx_max_pg_ring = 0;  in bnx2_set_rx_ring_size()
5407 	bp->rx_max_pg_ring_idx = 0;  in bnx2_set_rx_ring_size()
5408 	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {  in bnx2_set_rx_ring_size()
5409 		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;  in bnx2_set_rx_ring_size()
5415 		bp->rx_pg_ring_size = jumbo_size;  in bnx2_set_rx_ring_size()
5416 		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,  in bnx2_set_rx_ring_size()
5418 		bp->rx_max_pg_ring_idx =  in bnx2_set_rx_ring_size()
5419 			(bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5421 		bp->rx_copy_thresh = 0;  in bnx2_set_rx_ring_size()
5424 	bp->rx_buf_use_size = rx_size;  in bnx2_set_rx_ring_size()
5426 	bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +  in bnx2_set_rx_ring_size()
5428 	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;  in bnx2_set_rx_ring_size()
5429 	bp->rx_ring_size = size;  in bnx2_set_rx_ring_size()
5430 	bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);  in bnx2_set_rx_ring_size()
5431 	bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5435 bnx2_free_tx_skbs(struct bnx2 *bp)  in bnx2_free_tx_skbs()  argument
5439 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_skbs()
5440 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_skbs()
5457 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5468 				dma_unmap_page(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5475 		netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));  in bnx2_free_tx_skbs()
5480 bnx2_free_rx_skbs(struct bnx2 *bp)  in bnx2_free_rx_skbs()  argument
5484 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_skbs()
5485 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_skbs()
5492 		for (j = 0; j < bp->rx_max_ring_idx; j++) {  in bnx2_free_rx_skbs()
5499 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_rx_skbs()
5501 					 bp->rx_buf_use_size,  in bnx2_free_rx_skbs()
5508 		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)  in bnx2_free_rx_skbs()
5509 			bnx2_free_rx_page(bp, rxr, j);  in bnx2_free_rx_skbs()
5514 bnx2_free_skbs(struct bnx2 *bp)  in bnx2_free_skbs()  argument
5516 	bnx2_free_tx_skbs(bp);  in bnx2_free_skbs()
5517 	bnx2_free_rx_skbs(bp);  in bnx2_free_skbs()
5521 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_nic()  argument
5525 	rc = bnx2_reset_chip(bp, reset_code);  in bnx2_reset_nic()
5526 	bnx2_free_skbs(bp);  in bnx2_reset_nic()
5530 	if ((rc = bnx2_init_chip(bp)) != 0)  in bnx2_reset_nic()
5533 	bnx2_init_all_rings(bp);  in bnx2_reset_nic()
5538 bnx2_init_nic(struct bnx2 *bp, int reset_phy)  in bnx2_init_nic()  argument
5542 	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)  in bnx2_init_nic()
5545 	spin_lock_bh(&bp->phy_lock);  in bnx2_init_nic()
5546 	bnx2_init_phy(bp, reset_phy);  in bnx2_init_nic()
5547 	bnx2_set_link(bp);  in bnx2_init_nic()
5548 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_nic()
5549 		bnx2_remote_phy_event(bp);  in bnx2_init_nic()
5550 	spin_unlock_bh(&bp->phy_lock);  in bnx2_init_nic()
5555 bnx2_shutdown_chip(struct bnx2 *bp)  in bnx2_shutdown_chip()  argument
5559 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_shutdown_chip()
5561 	else if (bp->wol)  in bnx2_shutdown_chip()
5566 	return bnx2_reset_chip(bp, reset_code);  in bnx2_shutdown_chip()
5570 bnx2_test_registers(struct bnx2 *bp)  in bnx2_test_registers()  argument
5691 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_registers()
5705 		save_val = readl(bp->regview + offset);  in bnx2_test_registers()
5707 		writel(0, bp->regview + offset);  in bnx2_test_registers()
5709 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5718 		writel(0xffffffff, bp->regview + offset);  in bnx2_test_registers()
5720 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5729 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5733 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5741 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)  in bnx2_do_mem_test()  argument
5752 			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);  in bnx2_do_mem_test()
5754 			if (bnx2_reg_rd_ind(bp, start + offset) !=  in bnx2_do_mem_test()
5764 bnx2_test_memory(struct bnx2 *bp)  in bnx2_test_memory()  argument
5790 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_memory()
5796 		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,  in bnx2_test_memory()
5809 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)  in bnx2_run_loopback()  argument
5821 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;  in bnx2_run_loopback()
5830 		bp->loopback = MAC_LOOPBACK;  in bnx2_run_loopback()
5831 		bnx2_set_mac_loopback(bp);  in bnx2_run_loopback()
5834 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_run_loopback()
5837 		bp->loopback = PHY_LOOPBACK;  in bnx2_run_loopback()
5838 		bnx2_set_phy_loopback(bp);  in bnx2_run_loopback()
5843 	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);  in bnx2_run_loopback()
5844 	skb = netdev_alloc_skb(bp->dev, pkt_size);  in bnx2_run_loopback()
5848 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);  in bnx2_run_loopback()
5853 	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,  in bnx2_run_loopback()
5855 	if (dma_mapping_error(&bp->pdev->dev, map)) {  in bnx2_run_loopback()
5860 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5861 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5863 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5881 	BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);  in bnx2_run_loopback()
5882 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5886 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5887 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5889 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5893 	dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);  in bnx2_run_loopback()
5910 	dma_sync_single_for_cpu(&bp->pdev->dev,  in bnx2_run_loopback()
5912 		bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);  in bnx2_run_loopback()
5937 	bp->loopback = 0;  in bnx2_run_loopback()
5947 bnx2_test_loopback(struct bnx2 *bp)  in bnx2_test_loopback()  argument
5951 	if (!netif_running(bp->dev))  in bnx2_test_loopback()
5954 	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_test_loopback()
5955 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5956 	bnx2_init_phy(bp, 1);  in bnx2_test_loopback()
5957 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5958 	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))  in bnx2_test_loopback()
5960 	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))  in bnx2_test_loopback()
5969 bnx2_test_nvram(struct bnx2 *bp)  in bnx2_test_nvram()  argument
5976 	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)  in bnx2_test_nvram()
5985 	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)  in bnx2_test_nvram()
6004 bnx2_test_link(struct bnx2 *bp)  in bnx2_test_link()  argument
6008 	if (!netif_running(bp->dev))  in bnx2_test_link()
6011 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_test_link()
6012 		if (bp->link_up)  in bnx2_test_link()
6016 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_link()
6017 	bnx2_enable_bmsr1(bp);  in bnx2_test_link()
6018 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
6019 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
6020 	bnx2_disable_bmsr1(bp);  in bnx2_test_link()
6021 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_link()
6030 bnx2_test_intr(struct bnx2 *bp)  in bnx2_test_intr()  argument
6035 	if (!netif_running(bp->dev))  in bnx2_test_intr()
6038 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6041 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6042 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6045 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6061 bnx2_5706_serdes_has_link(struct bnx2 *bp)  in bnx2_5706_serdes_has_link()  argument
6065 	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)  in bnx2_5706_serdes_has_link()
6068 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);  in bnx2_5706_serdes_has_link()
6069 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);  in bnx2_5706_serdes_has_link()
6074 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_has_link()
6075 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6076 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6081 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);  in bnx2_5706_serdes_has_link()
6082 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6083 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6092 bnx2_5706_serdes_timer(struct bnx2 *bp)  in bnx2_5706_serdes_timer()  argument
6096 	spin_lock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6097 	if (bp->serdes_an_pending) {  in bnx2_5706_serdes_timer()
6098 		bp->serdes_an_pending--;  in bnx2_5706_serdes_timer()
6100 	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5706_serdes_timer()
6103 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6105 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6108 			if (bnx2_5706_serdes_has_link(bp)) {  in bnx2_5706_serdes_timer()
6111 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6112 				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6116 	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&  in bnx2_5706_serdes_timer()
6117 		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {  in bnx2_5706_serdes_timer()
6120 		bnx2_write_phy(bp, 0x17, 0x0f01);  in bnx2_5706_serdes_timer()
6121 		bnx2_read_phy(bp, 0x15, &phy2);  in bnx2_5706_serdes_timer()
6125 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6127 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6129 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6132 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6137 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_timer()
6138 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6139 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6141 		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {  in bnx2_5706_serdes_timer()
6142 			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {  in bnx2_5706_serdes_timer()
6143 				bnx2_5706s_force_link_dn(bp, 1);  in bnx2_5706_serdes_timer()
6144 				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_5706_serdes_timer()
6146 				bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6147 		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))  in bnx2_5706_serdes_timer()
6148 			bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6150 	spin_unlock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6154 bnx2_5708_serdes_timer(struct bnx2 *bp)  in bnx2_5708_serdes_timer()  argument
6156 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_5708_serdes_timer()
6159 	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {  in bnx2_5708_serdes_timer()
6160 		bp->serdes_an_pending = 0;  in bnx2_5708_serdes_timer()
6164 	spin_lock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6165 	if (bp->serdes_an_pending)  in bnx2_5708_serdes_timer()
6166 		bp->serdes_an_pending--;  in bnx2_5708_serdes_timer()
6167 	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5708_serdes_timer()
6170 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5708_serdes_timer()
6172 			bnx2_enable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6173 			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;  in bnx2_5708_serdes_timer()
6175 			bnx2_disable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6176 			bp->serdes_an_pending = 2;  in bnx2_5708_serdes_timer()
6177 			bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6181 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6183 	spin_unlock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6189 	struct bnx2 *bp = from_timer(bp, t, timer);  in bnx2_timer()  local
6191 	if (!netif_running(bp->dev))  in bnx2_timer()
6194 	if (atomic_read(&bp->intr_sem) != 0)  in bnx2_timer()
6197 	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==  in bnx2_timer()
6199 		bnx2_chk_missed_msi(bp);  in bnx2_timer()
6201 	bnx2_send_heart_beat(bp);  in bnx2_timer()
6203 	bp->stats_blk->stat_FwRxDrop =  in bnx2_timer()
6204 		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);  in bnx2_timer()
6207 	if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)  in bnx2_timer()
6208 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6211 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_timer()
6212 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_timer()
6213 			bnx2_5706_serdes_timer(bp);  in bnx2_timer()
6215 			bnx2_5708_serdes_timer(bp);  in bnx2_timer()
6219 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_timer()
6223 bnx2_request_irq(struct bnx2 *bp)  in bnx2_request_irq()  argument
6229 	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)  in bnx2_request_irq()
6234 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_request_irq()
6235 		irq = &bp->irq_tbl[i];  in bnx2_request_irq()
6237 				 &bp->bnx2_napi[i]);  in bnx2_request_irq()
6246 __bnx2_free_irq(struct bnx2 *bp)  in __bnx2_free_irq()  argument
6251 	for (i = 0; i < bp->irq_nvecs; i++) {  in __bnx2_free_irq()
6252 		irq = &bp->irq_tbl[i];  in __bnx2_free_irq()
6254 			free_irq(irq->vector, &bp->bnx2_napi[i]);  in __bnx2_free_irq()
6260 bnx2_free_irq(struct bnx2 *bp)  in bnx2_free_irq()  argument
6263 	__bnx2_free_irq(bp);  in bnx2_free_irq()
6264 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_free_irq()
6265 		pci_disable_msi(bp->pdev);  in bnx2_free_irq()
6266 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_free_irq()
6267 		pci_disable_msix(bp->pdev);  in bnx2_free_irq()
6269 	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);  in bnx2_free_irq()
6273 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)  in bnx2_enable_msix()  argument
6277 	struct net_device *dev = bp->dev;  in bnx2_enable_msix()
6278 	const int len = sizeof(bp->irq_tbl[0].name);  in bnx2_enable_msix()
6280 	bnx2_setup_msix_tbl(bp);  in bnx2_enable_msix()
6281 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6282 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6283 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6287 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6298 	total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,  in bnx2_enable_msix()
6307 	bp->irq_nvecs = msix_vecs;  in bnx2_enable_msix()
6308 	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_enable_msix()
6310 		bp->irq_tbl[i].vector = msix_ent[i].vector;  in bnx2_enable_msix()
6311 		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);  in bnx2_enable_msix()
6312 		bp->irq_tbl[i].handler = bnx2_msi_1shot;  in bnx2_enable_msix()
6317 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)  in bnx2_setup_int_mode()  argument
6322 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6323 		msix_vecs = max(cpus + 1, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6324 	else if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6325 		msix_vecs = max(cpus, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6327 		msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6331 	bp->irq_tbl[0].handler = bnx2_interrupt;  in bnx2_setup_int_mode()
6332 	strcpy(bp->irq_tbl[0].name, bp->dev->name);  in bnx2_setup_int_mode()
6333 	bp->irq_nvecs = 1;  in bnx2_setup_int_mode()
6334 	bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6336 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)  in bnx2_setup_int_mode()
6337 		bnx2_enable_msix(bp, msix_vecs);  in bnx2_setup_int_mode()
6339 	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&  in bnx2_setup_int_mode()
6340 	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_setup_int_mode()
6341 		if (pci_enable_msi(bp->pdev) == 0) {  in bnx2_setup_int_mode()
6342 			bp->flags |= BNX2_FLAG_USING_MSI;  in bnx2_setup_int_mode()
6343 			if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_int_mode()
6344 				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_setup_int_mode()
6345 				bp->irq_tbl[0].handler = bnx2_msi_1shot;  in bnx2_setup_int_mode()
6347 				bp->irq_tbl[0].handler = bnx2_msi;  in bnx2_setup_int_mode()
6349 			bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6353 	if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6354 		bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);  in bnx2_setup_int_mode()
6356 		bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6358 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6359 		bp->num_rx_rings = bp->irq_nvecs;  in bnx2_setup_int_mode()
6361 		bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6363 	netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);  in bnx2_setup_int_mode()
6365 	return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);  in bnx2_setup_int_mode()
6372 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_open()  local
6375 	rc = bnx2_request_firmware(bp);  in bnx2_open()
6381 	bnx2_disable_int(bp);  in bnx2_open()
6383 	rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_open()
6386 	bnx2_init_napi(bp);  in bnx2_open()
6387 	bnx2_napi_enable(bp);  in bnx2_open()
6388 	rc = bnx2_alloc_mem(bp);  in bnx2_open()
6392 	rc = bnx2_request_irq(bp);  in bnx2_open()
6396 	rc = bnx2_init_nic(bp, 1);  in bnx2_open()
6400 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_open()
6402 	atomic_set(&bp->intr_sem, 0);  in bnx2_open()
6404 	memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));  in bnx2_open()
6406 	bnx2_enable_int(bp);  in bnx2_open()
6408 	if (bp->flags & BNX2_FLAG_USING_MSI) {  in bnx2_open()
6412 		if (bnx2_test_intr(bp) != 0) {  in bnx2_open()
6413 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report …  in bnx2_open()
6415 			bnx2_disable_int(bp);  in bnx2_open()
6416 			bnx2_free_irq(bp);  in bnx2_open()
6418 			bnx2_setup_int_mode(bp, 1);  in bnx2_open()
6420 			rc = bnx2_init_nic(bp, 0);  in bnx2_open()
6423 				rc = bnx2_request_irq(bp);  in bnx2_open()
6426 				del_timer_sync(&bp->timer);  in bnx2_open()
6429 			bnx2_enable_int(bp);  in bnx2_open()
6432 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_open()
6434 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_open()
6442 	bnx2_napi_disable(bp);  in bnx2_open()
6443 	bnx2_free_skbs(bp);  in bnx2_open()
6444 	bnx2_free_irq(bp);  in bnx2_open()
6445 	bnx2_free_mem(bp);  in bnx2_open()
6446 	bnx2_del_napi(bp);  in bnx2_open()
6447 	bnx2_release_firmware(bp);  in bnx2_open()
6454 	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);  in bnx2_reset_task()  local
6459 	if (!netif_running(bp->dev)) {  in bnx2_reset_task()
6464 	bnx2_netif_stop(bp, true);  in bnx2_reset_task()
6466 	pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);  in bnx2_reset_task()
6469 		pci_restore_state(bp->pdev);  in bnx2_reset_task()
6470 		pci_save_state(bp->pdev);  in bnx2_reset_task()
6472 	rc = bnx2_init_nic(bp, 1);  in bnx2_reset_task()
6474 		netdev_err(bp->dev, "failed to reset NIC, closing\n");  in bnx2_reset_task()
6475 		bnx2_napi_enable(bp);  in bnx2_reset_task()
6476 		dev_close(bp->dev);  in bnx2_reset_task()
6481 	atomic_set(&bp->intr_sem, 1);  in bnx2_reset_task()
6482 	bnx2_netif_start(bp, true);  in bnx2_reset_task()
6489 bnx2_dump_ftq(struct bnx2 *bp)  in bnx2_dump_ftq()  argument
6493 	struct net_device *dev = bp->dev;  in bnx2_dump_ftq()
6517 			   bnx2_reg_rd_ind(bp, ftq_arr[i].off));  in bnx2_dump_ftq()
6522 			   reg, bnx2_reg_rd_ind(bp, reg),  in bnx2_dump_ftq()
6523 			   bnx2_reg_rd_ind(bp, reg + 4),  in bnx2_dump_ftq()
6524 			   bnx2_reg_rd_ind(bp, reg + 8),  in bnx2_dump_ftq()
6525 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6526 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6527 			   bnx2_reg_rd_ind(bp, reg + 0x20));  in bnx2_dump_ftq()
6532 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6537 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6538 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6540 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6541 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6545 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6546 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6547 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6556 bnx2_dump_state(struct bnx2 *bp)  in bnx2_dump_state()  argument
6558 	struct net_device *dev = bp->dev;  in bnx2_dump_state()
6561 	pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);  in bnx2_dump_state()
6563 		   atomic_read(&bp->intr_sem), val1);  in bnx2_dump_state()
6564 	pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);  in bnx2_dump_state()
6565 	pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);  in bnx2_dump_state()
6568 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6569 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6571 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6573 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6574 	if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_dump_state()
6576 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
6582 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_tx_timeout()  local
6584 	bnx2_dump_ftq(bp);  in bnx2_tx_timeout()
6585 	bnx2_dump_state(bp);  in bnx2_tx_timeout()
6586 	bnx2_dump_mcp_state(bp);  in bnx2_tx_timeout()
6589 	schedule_work(&bp->reset_task);  in bnx2_tx_timeout()
6599 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_start_xmit()  local
6612 	bnapi = &bp->bnx2_napi[i];  in bnx2_start_xmit()
6616 	if (unlikely(bnx2_tx_avail(bp, txr) <  in bnx2_start_xmit()
6671 	mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);  in bnx2_start_xmit()
6672 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_start_xmit()
6700 		mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,  in bnx2_start_xmit()
6702 		if (dma_mapping_error(&bp->pdev->dev, mapping))  in bnx2_start_xmit()
6723 	BNX2_WR16(bp, txr->tx_bidx_addr, prod);  in bnx2_start_xmit()
6724 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
6730 	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {  in bnx2_start_xmit()
6739 		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)  in bnx2_start_xmit()
6753 	dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6761 		dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6774 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_close()  local
6776 	bnx2_disable_int_sync(bp);  in bnx2_close()
6777 	bnx2_napi_disable(bp);  in bnx2_close()
6779 	del_timer_sync(&bp->timer);  in bnx2_close()
6780 	bnx2_shutdown_chip(bp);  in bnx2_close()
6781 	bnx2_free_irq(bp);  in bnx2_close()
6782 	bnx2_free_skbs(bp);  in bnx2_close()
6783 	bnx2_free_mem(bp);  in bnx2_close()
6784 	bnx2_del_napi(bp);  in bnx2_close()
6785 	bp->link_up = 0;  in bnx2_close()
6786 	netif_carrier_off(bp->dev);  in bnx2_close()
6791 bnx2_save_stats(struct bnx2 *bp)  in bnx2_save_stats()  argument
6793 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_save_stats()
6794 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_save_stats()
6818 	GET_64BIT_NET_STATS64(bp->stats_blk->ctr) +		\
6819 	GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6822 	(unsigned long) (bp->stats_blk->ctr +			\
6823 			 bp->temp_stats_blk->ctr)
6828 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_stats64()  local
6830 	if (!bp->stats_blk)  in bnx2_get_stats64()
6877 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_get_stats64()
6878 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_stats64()
6903 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link_ksettings()  local
6908 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_get_link_ksettings()
6911 	} else if (bp->phy_port == PORT_FIBRE)  in bnx2_get_link_ksettings()
6919 		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_get_link_ksettings()
6931 	spin_lock_bh(&bp->phy_lock);  in bnx2_get_link_ksettings()
6932 	cmd->base.port = bp->phy_port;  in bnx2_get_link_ksettings()
6933 	advertising = bp->advertising;  in bnx2_get_link_ksettings()
6935 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_get_link_ksettings()
6942 		cmd->base.speed = bp->line_speed;  in bnx2_get_link_ksettings()
6943 		cmd->base.duplex = bp->duplex;  in bnx2_get_link_ksettings()
6944 		if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {  in bnx2_get_link_ksettings()
6945 			if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)  in bnx2_get_link_ksettings()
6955 	spin_unlock_bh(&bp->phy_lock);  in bnx2_get_link_ksettings()
6957 	cmd->base.phy_address = bp->phy_addr;  in bnx2_get_link_ksettings()
6971 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_link_ksettings()  local
6972 	u8 autoneg = bp->autoneg;  in bnx2_set_link_ksettings()
6973 	u8 req_duplex = bp->req_duplex;  in bnx2_set_link_ksettings()
6974 	u16 req_line_speed = bp->req_line_speed;  in bnx2_set_link_ksettings()
6975 	u32 advertising = bp->advertising;  in bnx2_set_link_ksettings()
6978 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_link_ksettings()
6983 	if (cmd->base.port != bp->phy_port &&  in bnx2_set_link_ksettings()
6984 	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))  in bnx2_set_link_ksettings()
6990 	if (!netif_running(dev) && cmd->base.port != bp->phy_port)  in bnx2_set_link_ksettings()
7020 			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_set_link_ksettings()
7031 	bp->autoneg = autoneg;  in bnx2_set_link_ksettings()
7032 	bp->advertising = advertising;  in bnx2_set_link_ksettings()
7033 	bp->req_line_speed = req_line_speed;  in bnx2_set_link_ksettings()
7034 	bp->req_duplex = req_duplex;  in bnx2_set_link_ksettings()
7041 		err = bnx2_setup_phy(bp, cmd->base.port);  in bnx2_set_link_ksettings()
7044 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_link_ksettings()
7052 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_drvinfo()  local
7056 	strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));  in bnx2_get_drvinfo()
7057 	strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));  in bnx2_get_drvinfo()
7073 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_regs()  local
7103 	if (!netif_running(bp->dev))  in bnx2_get_regs()
7110 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7123 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_wol()  local
7125 	if (bp->flags & BNX2_FLAG_NO_WOL) {  in bnx2_get_wol()
7131 		if (bp->wol)  in bnx2_get_wol()
7142 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_wol()  local
7148 		if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_set_wol()
7151 		bp->wol = 1;  in bnx2_set_wol()
7154 		bp->wol = 0;  in bnx2_set_wol()
7157 	device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_set_wol()
7165 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_nway_reset()  local
7171 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_nway_reset()
7175 	spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7177 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_nway_reset()
7180 		rc = bnx2_setup_remote_phy(bp, bp->phy_port);  in bnx2_nway_reset()
7181 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7186 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_nway_reset()
7187 		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_nway_reset()
7188 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7192 		spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7194 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_nway_reset()
7195 		bp->serdes_an_pending = 1;  in bnx2_nway_reset()
7196 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_nway_reset()
7199 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_nway_reset()
7201 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);  in bnx2_nway_reset()
7203 	spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7211 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link()  local
7213 	return bp->link_up;  in bnx2_get_link()
7219 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom_len()  local
7221 	if (!bp->flash_info)  in bnx2_get_eeprom_len()
7224 	return (int) bp->flash_size;  in bnx2_get_eeprom_len()
7231 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom()  local
7236 	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_get_eeprom()
7245 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_eeprom()  local
7250 	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_set_eeprom()
7258 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_coalesce()  local
7262 	coal->rx_coalesce_usecs = bp->rx_ticks;  in bnx2_get_coalesce()
7263 	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;  in bnx2_get_coalesce()
7264 	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;  in bnx2_get_coalesce()
7265 	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;  in bnx2_get_coalesce()
7267 	coal->tx_coalesce_usecs = bp->tx_ticks;  in bnx2_get_coalesce()
7268 	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;  in bnx2_get_coalesce()
7269 	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;  in bnx2_get_coalesce()
7270 	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;  in bnx2_get_coalesce()
7272 	coal->stats_block_coalesce_usecs = bp->stats_ticks;  in bnx2_get_coalesce()
7280 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_coalesce()  local
7282 	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;  in bnx2_set_coalesce()
7283 	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;  in bnx2_set_coalesce()
7285 	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;  in bnx2_set_coalesce()
7286 	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7288 	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7289 	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7291 	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7292 	if (bp->rx_quick_cons_trip_int > 0xff)  in bnx2_set_coalesce()
7293 		bp->rx_quick_cons_trip_int = 0xff;  in bnx2_set_coalesce()
7295 	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;  in bnx2_set_coalesce()
7296 	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;  in bnx2_set_coalesce()
7298 	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;  in bnx2_set_coalesce()
7299 	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7301 	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7302 	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7304 	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7305 	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =  in bnx2_set_coalesce()
7308 	bp->stats_ticks = coal->stats_block_coalesce_usecs;  in bnx2_set_coalesce()
7309 	if (bp->flags & BNX2_FLAG_BROKEN_STATS) {  in bnx2_set_coalesce()
7310 		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)  in bnx2_set_coalesce()
7311 			bp->stats_ticks = USEC_PER_SEC;  in bnx2_set_coalesce()
7313 	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)  in bnx2_set_coalesce()
7314 		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7315 	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7317 	if (netif_running(bp->dev)) {  in bnx2_set_coalesce()
7318 		bnx2_netif_stop(bp, true);  in bnx2_set_coalesce()
7319 		bnx2_init_nic(bp, 0);  in bnx2_set_coalesce()
7320 		bnx2_netif_start(bp, true);  in bnx2_set_coalesce()
7329 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ringparam()  local
7334 	ering->rx_pending = bp->rx_ring_size;  in bnx2_get_ringparam()
7335 	ering->rx_jumbo_pending = bp->rx_pg_ring_size;  in bnx2_get_ringparam()
7338 	ering->tx_pending = bp->tx_ring_size;  in bnx2_get_ringparam()
7342 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)  in bnx2_change_ring_size()  argument
7344 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7346 		bnx2_save_stats(bp);  in bnx2_change_ring_size()
7348 		bnx2_netif_stop(bp, true);  in bnx2_change_ring_size()
7349 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_change_ring_size()
7351 			bnx2_free_irq(bp);  in bnx2_change_ring_size()
7352 			bnx2_del_napi(bp);  in bnx2_change_ring_size()
7354 			__bnx2_free_irq(bp);  in bnx2_change_ring_size()
7356 		bnx2_free_skbs(bp);  in bnx2_change_ring_size()
7357 		bnx2_free_mem(bp);  in bnx2_change_ring_size()
7360 	bnx2_set_rx_ring_size(bp, rx);  in bnx2_change_ring_size()
7361 	bp->tx_ring_size = tx;  in bnx2_change_ring_size()
7363 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7367 			rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_change_ring_size()
7368 			bnx2_init_napi(bp);  in bnx2_change_ring_size()
7372 			rc = bnx2_alloc_mem(bp);  in bnx2_change_ring_size()
7375 			rc = bnx2_request_irq(bp);  in bnx2_change_ring_size()
7378 			rc = bnx2_init_nic(bp, 0);  in bnx2_change_ring_size()
7381 			bnx2_napi_enable(bp);  in bnx2_change_ring_size()
7382 			dev_close(bp->dev);  in bnx2_change_ring_size()
7386 		mutex_lock(&bp->cnic_lock);  in bnx2_change_ring_size()
7388 		if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)  in bnx2_change_ring_size()
7389 			bnx2_setup_cnic_irq_info(bp);  in bnx2_change_ring_size()
7390 		mutex_unlock(&bp->cnic_lock);  in bnx2_change_ring_size()
7392 		bnx2_netif_start(bp, true);  in bnx2_change_ring_size()
7400 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_ringparam()  local
7409 	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,  in bnx2_set_ringparam()
7417 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_pauseparam()  local
7419 	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);  in bnx2_get_pauseparam()
7420 	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);  in bnx2_get_pauseparam()
7421 	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);  in bnx2_get_pauseparam()
7427 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_pauseparam()  local
7429 	bp->req_flow_ctrl = 0;  in bnx2_set_pauseparam()
7431 		bp->req_flow_ctrl |= FLOW_CTRL_RX;  in bnx2_set_pauseparam()
7433 		bp->req_flow_ctrl |= FLOW_CTRL_TX;  in bnx2_set_pauseparam()
7436 		bp->autoneg |= AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7439 		bp->autoneg &= ~AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7443 		spin_lock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7444 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_set_pauseparam()
7445 		spin_unlock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7605 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_self_test()  local
7611 		bnx2_netif_stop(bp, true);  in bnx2_self_test()
7612 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);  in bnx2_self_test()
7613 		bnx2_free_skbs(bp);  in bnx2_self_test()
7615 		if (bnx2_test_registers(bp) != 0) {  in bnx2_self_test()
7619 		if (bnx2_test_memory(bp) != 0) {  in bnx2_self_test()
7623 		if ((buf[2] = bnx2_test_loopback(bp)) != 0)  in bnx2_self_test()
7626 		if (!netif_running(bp->dev))  in bnx2_self_test()
7627 			bnx2_shutdown_chip(bp);  in bnx2_self_test()
7629 			bnx2_init_nic(bp, 1);  in bnx2_self_test()
7630 			bnx2_netif_start(bp, true);  in bnx2_self_test()
7635 			if (bp->link_up)  in bnx2_self_test()
7641 	if (bnx2_test_nvram(bp) != 0) {  in bnx2_self_test()
7645 	if (bnx2_test_intr(bp) != 0) {  in bnx2_self_test()
7650 	if (bnx2_test_link(bp) != 0) {  in bnx2_self_test()
7676 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ethtool_stats()  local
7678 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_get_ethtool_stats()
7679 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_get_ethtool_stats()
7687 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_get_ethtool_stats()
7688 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||  in bnx2_get_ethtool_stats()
7689 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||  in bnx2_get_ethtool_stats()
7690 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_ethtool_stats()
7722 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_phys_id()  local
7726 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7727 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7731 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7740 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7744 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7745 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
7755 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_features()  local
7764 	    !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&  in bnx2_set_features()
7766 		bnx2_netif_stop(bp, false);  in bnx2_set_features()
7769 		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);  in bnx2_set_features()
7770 		bnx2_netif_start(bp, false);  in bnx2_set_features()
7780 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_channels()  local
7784 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_get_channels()
7793 	channels->rx_count = bp->num_rx_rings;  in bnx2_get_channels()
7794 	channels->tx_count = bp->num_tx_rings;  in bnx2_get_channels()
7802 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_channels()  local
7807 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_set_channels()
7815 	bp->num_req_rx_rings = channels->rx_count;  in bnx2_set_channels()
7816 	bp->num_req_tx_rings = channels->tx_count;  in bnx2_set_channels()
7819 		rc = bnx2_change_ring_size(bp, bp->rx_ring_size,  in bnx2_set_channels()
7820 					   bp->tx_ring_size, true);  in bnx2_set_channels()
7858 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_ioctl()  local
7863 		data->phy_id = bp->phy_addr;  in bnx2_ioctl()
7869 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7875 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7876 		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);  in bnx2_ioctl()
7877 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7885 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7891 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7892 		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);  in bnx2_ioctl()
7893 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7909 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mac_addr()  local
7916 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_change_mac_addr()
7925 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mtu()  local
7928 	return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,  in bnx2_change_mtu()
7936 	struct bnx2 *bp = netdev_priv(dev);  in poll_bnx2()  local
7939 	for (i = 0; i < bp->irq_nvecs; i++) {  in poll_bnx2()
7940 		struct bnx2_irq *irq = &bp->irq_tbl[i];  in poll_bnx2()
7943 		irq->handler(irq->vector, &bp->bnx2_napi[i]);  in poll_bnx2()
7950 bnx2_get_5709_media(struct bnx2 *bp)  in bnx2_get_5709_media()  argument
7952 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7959 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7968 	if (bp->func == 0) {  in bnx2_get_5709_media()
7973 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7981 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7988 bnx2_get_pci_speed(struct bnx2 *bp)  in bnx2_get_pci_speed()  argument
7992 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7996 		bp->flags |= BNX2_FLAG_PCIX;  in bnx2_get_pci_speed()
7998 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
8003 			bp->bus_speed_mhz = 133;  in bnx2_get_pci_speed()
8007 			bp->bus_speed_mhz = 100;  in bnx2_get_pci_speed()
8012 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8017 			bp->bus_speed_mhz = 50;  in bnx2_get_pci_speed()
8023 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8029 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8031 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8035 		bp->flags |= BNX2_FLAG_PCI_32BIT;  in bnx2_get_pci_speed()
8040 bnx2_read_vpd_fw_ver(struct bnx2 *bp)  in bnx2_read_vpd_fw_ver()  argument
8054 	rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,  in bnx2_read_vpd_fw_ver()
8100 	memcpy(bp->fw_version, &data[j], len);  in bnx2_read_vpd_fw_ver()
8101 	bp->fw_version[len] = ' ';  in bnx2_read_vpd_fw_ver()
8110 	struct bnx2 *bp;  in bnx2_init_board()  local
8117 	bp = netdev_priv(dev);  in bnx2_init_board()
8119 	bp->flags = 0;  in bnx2_init_board()
8120 	bp->phy_flags = 0;  in bnx2_init_board()
8122 	bp->temp_stats_blk =  in bnx2_init_board()
8125 	if (!bp->temp_stats_blk) {  in bnx2_init_board()
8152 	bp->pm_cap = pdev->pm_cap;  in bnx2_init_board()
8153 	if (bp->pm_cap == 0) {  in bnx2_init_board()
8160 	bp->dev = dev;  in bnx2_init_board()
8161 	bp->pdev = pdev;  in bnx2_init_board()
8163 	spin_lock_init(&bp->phy_lock);  in bnx2_init_board()
8164 	spin_lock_init(&bp->indirect_lock);  in bnx2_init_board()
8166 	mutex_init(&bp->cnic_lock);  in bnx2_init_board()
8168 	INIT_WORK(&bp->reset_task, bnx2_reset_task);  in bnx2_init_board()
8170 	bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +  in bnx2_init_board()
8172 	if (!bp->regview) {  in bnx2_init_board()
8182 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8186 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8188 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_board()
8194 		bp->flags |= BNX2_FLAG_PCIE;  in bnx2_init_board()
8195 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_board()
8196 			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;  in bnx2_init_board()
8201 			bp->flags |= BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8204 		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);  in bnx2_init_board()
8205 		if (bp->pcix_cap == 0) {  in bnx2_init_board()
8211 		bp->flags |= BNX2_FLAG_BROKEN_STATS;  in bnx2_init_board()
8214 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8215 	    BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {  in bnx2_init_board()
8217 			bp->flags |= BNX2_FLAG_MSIX_CAP;  in bnx2_init_board()
8220 	if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&  in bnx2_init_board()
8221 	    BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {  in bnx2_init_board()
8223 			bp->flags |= BNX2_FLAG_MSI_CAP;  in bnx2_init_board()
8227 	if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8246 	if (!(bp->flags & BNX2_FLAG_PCIE))  in bnx2_init_board()
8247 		bnx2_get_pci_speed(bp);  in bnx2_init_board()
8250 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8251 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8253 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()
8254 	} else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&  in bnx2_init_board()
8255 		!(bp->flags & BNX2_FLAG_PCIX)) {  in bnx2_init_board()
8262 	bnx2_init_nvram(bp);  in bnx2_init_board()
8264 	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);  in bnx2_init_board()
8266 	if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)  in bnx2_init_board()
8267 		bp->func = 1;  in bnx2_init_board()
8271 		u32 off = bp->func << 2;  in bnx2_init_board()
8273 		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);  in bnx2_init_board()
8275 		bp->shmem_base = HOST_VIEW_SHMEM_BASE;  in bnx2_init_board()
8280 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);  in bnx2_init_board()
8289 	bnx2_read_vpd_fw_ver(bp);  in bnx2_init_board()
8291 	j = strlen(bp->fw_version);  in bnx2_init_board()
8292 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);  in bnx2_init_board()
8297 			bp->fw_version[j++] = 'b';  in bnx2_init_board()
8298 			bp->fw_version[j++] = 'c';  in bnx2_init_board()
8299 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8304 				bp->fw_version[j++] = (num / k) + '0';  in bnx2_init_board()
8309 			bp->fw_version[j++] = '.';  in bnx2_init_board()
8311 	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_init_board()
8313 		bp->wol = 1;  in bnx2_init_board()
8316 		bp->flags |= BNX2_FLAG_ASF_ENABLE;  in bnx2_init_board()
8319 			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8325 	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8329 		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);  in bnx2_init_board()
8332 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8334 			reg = bnx2_reg_rd_ind(bp, addr + i * 4);  in bnx2_init_board()
8336 			memcpy(&bp->fw_version[j], &reg, 4);  in bnx2_init_board()
8341 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);  in bnx2_init_board()
8342 	bp->mac_addr[0] = (u8) (reg >> 8);  in bnx2_init_board()
8343 	bp->mac_addr[1] = (u8) reg;  in bnx2_init_board()
8345 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);  in bnx2_init_board()
8346 	bp->mac_addr[2] = (u8) (reg >> 24);  in bnx2_init_board()
8347 	bp->mac_addr[3] = (u8) (reg >> 16);  in bnx2_init_board()
8348 	bp->mac_addr[4] = (u8) (reg >> 8);  in bnx2_init_board()
8349 	bp->mac_addr[5] = (u8) reg;  in bnx2_init_board()
8351 	bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;  in bnx2_init_board()
8352 	bnx2_set_rx_ring_size(bp, 255);  in bnx2_init_board()
8354 	bp->tx_quick_cons_trip_int = 2;  in bnx2_init_board()
8355 	bp->tx_quick_cons_trip = 20;  in bnx2_init_board()
8356 	bp->tx_ticks_int = 18;  in bnx2_init_board()
8357 	bp->tx_ticks = 80;  in bnx2_init_board()
8359 	bp->rx_quick_cons_trip_int = 2;  in bnx2_init_board()
8360 	bp->rx_quick_cons_trip = 12;  in bnx2_init_board()
8361 	bp->rx_ticks_int = 18;  in bnx2_init_board()
8362 	bp->rx_ticks = 18;  in bnx2_init_board()
8364 	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_init_board()
8366 	bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_init_board()
8368 	bp->phy_addr = 1;  in bnx2_init_board()
8376 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_board()
8377 		bnx2_get_5709_media(bp);  in bnx2_init_board()
8378 	else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)  in bnx2_init_board()
8379 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_init_board()
8381 	bp->phy_port = PORT_TP;  in bnx2_init_board()
8382 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_board()
8383 		bp->phy_port = PORT_FIBRE;  in bnx2_init_board()
8384 		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_board()
8386 			bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8387 			bp->wol = 0;  in bnx2_init_board()
8389 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {  in bnx2_init_board()
8396 				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;  in bnx2_init_board()
8398 			bp->phy_addr = 2;  in bnx2_init_board()
8400 				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;  in bnx2_init_board()
8402 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||  in bnx2_init_board()
8403 		   BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8404 		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;  in bnx2_init_board()
8405 	else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8406 		 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||  in bnx2_init_board()
8407 		  BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))  in bnx2_init_board()
8408 		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;  in bnx2_init_board()
8410 	bnx2_init_fw_cap(bp);  in bnx2_init_board()
8412 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_board()
8413 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_board()
8414 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||  in bnx2_init_board()
8415 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()
8416 		bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8417 		bp->wol = 0;  in bnx2_init_board()
8420 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_init_board()
8421 		device_set_wakeup_capable(&bp->pdev->dev, false);  in bnx2_init_board()
8423 		device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_init_board()
8425 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8426 		bp->tx_quick_cons_trip_int =  in bnx2_init_board()
8427 			bp->tx_quick_cons_trip;  in bnx2_init_board()
8428 		bp->tx_ticks_int = bp->tx_ticks;  in bnx2_init_board()
8429 		bp->rx_quick_cons_trip_int =  in bnx2_init_board()
8430 			bp->rx_quick_cons_trip;  in bnx2_init_board()
8431 		bp->rx_ticks_int = bp->rx_ticks;  in bnx2_init_board()
8432 		bp->comp_prod_trip_int = bp->comp_prod_trip;  in bnx2_init_board()
8433 		bp->com_ticks_int = bp->com_ticks;  in bnx2_init_board()
8434 		bp->cmd_ticks_int = bp->cmd_ticks;  in bnx2_init_board()
8447 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {  in bnx2_init_board()
8463 	bnx2_set_default_link(bp);  in bnx2_init_board()
8464 	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in bnx2_init_board()
8466 	timer_setup(&bp->timer, bnx2_timer, 0);  in bnx2_init_board()
8467 	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);  in bnx2_init_board()
8470 	if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)  in bnx2_init_board()
8471 		bp->cnic_eth_dev.max_iscsi_conn =  in bnx2_init_board()
8472 			(bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &  in bnx2_init_board()
8474 	bp->cnic_probe = bnx2_cnic_probe;  in bnx2_init_board()
8481 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_init_board()
8483 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8486 	pci_iounmap(pdev, bp->regview);  in bnx2_init_board()
8487 	bp->regview = NULL;  in bnx2_init_board()
8496 	kfree(bp->temp_stats_blk);  in bnx2_init_board()
8502 bnx2_bus_string(struct bnx2 *bp, char *str)  in bnx2_bus_string()  argument
8506 	if (bp->flags & BNX2_FLAG_PCIE) {  in bnx2_bus_string()
8510 		if (bp->flags & BNX2_FLAG_PCIX)  in bnx2_bus_string()
8512 		if (bp->flags & BNX2_FLAG_PCI_32BIT)  in bnx2_bus_string()
8516 		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);  in bnx2_bus_string()
8522 bnx2_del_napi(struct bnx2 *bp)  in bnx2_del_napi()  argument
8526 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_del_napi()
8527 		netif_napi_del(&bp->bnx2_napi[i].napi);  in bnx2_del_napi()
8531 bnx2_init_napi(struct bnx2 *bp)  in bnx2_init_napi()  argument
8535 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_init_napi()
8536 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_init_napi()
8544 		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);  in bnx2_init_napi()
8545 		bnapi->bp = bp;  in bnx2_init_napi()
8571 	struct bnx2 *bp;  in bnx2_init_one()  local
8579 	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);  in bnx2_init_one()
8591 	bp = netdev_priv(dev);  in bnx2_init_one()
8602 		bnx2_wait_dma_complete(bp);  in bnx2_init_one()
8604 	memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);  in bnx2_init_one()
8610 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_one()
8620 	if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_init_one()
8630 		    ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',  in bnx2_init_one()
8631 		    ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),  in bnx2_init_one()
8632 		    bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),  in bnx2_init_one()
8638 	pci_iounmap(pdev, bp->regview);  in bnx2_init_one()
8651 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_remove_one()  local
8655 	del_timer_sync(&bp->timer);  in bnx2_remove_one()
8656 	cancel_work_sync(&bp->reset_task);  in bnx2_remove_one()
8658 	pci_iounmap(bp->pdev, bp->regview);  in bnx2_remove_one()
8661 	kfree(bp->temp_stats_blk);  in bnx2_remove_one()
8663 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_remove_one()
8665 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_remove_one()
8668 	bnx2_release_firmware(bp);  in bnx2_remove_one()
8682 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_suspend()  local
8685 		cancel_work_sync(&bp->reset_task);  in bnx2_suspend()
8686 		bnx2_netif_stop(bp, true);  in bnx2_suspend()
8688 		del_timer_sync(&bp->timer);  in bnx2_suspend()
8689 		bnx2_shutdown_chip(bp);  in bnx2_suspend()
8690 		__bnx2_free_irq(bp);  in bnx2_suspend()
8691 		bnx2_free_skbs(bp);  in bnx2_suspend()
8693 	bnx2_setup_wol(bp);  in bnx2_suspend()
8702 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_resume()  local
8707 	bnx2_set_power_state(bp, PCI_D0);  in bnx2_resume()
8709 	bnx2_request_irq(bp);  in bnx2_resume()
8710 	bnx2_init_nic(bp, 1);  in bnx2_resume()
8711 	bnx2_netif_start(bp, true);  in bnx2_resume()
8735 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_error_detected()  local
8746 		bnx2_netif_stop(bp, true);  in bnx2_io_error_detected()
8747 		del_timer_sync(&bp->timer);  in bnx2_io_error_detected()
8748 		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_io_error_detected()
8767 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_slot_reset()  local
8781 			err = bnx2_init_nic(bp, 1);  in bnx2_io_slot_reset()
8788 		bnx2_napi_enable(bp);  in bnx2_io_slot_reset()
8793 	if (!(bp->flags & BNX2_FLAG_AER_ENABLED))  in bnx2_io_slot_reset()
8816 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_resume()  local
8820 		bnx2_netif_start(bp, true);  in bnx2_io_resume()
8829 	struct bnx2 *bp;  in bnx2_shutdown()  local
8834 	bp = netdev_priv(dev);  in bnx2_shutdown()
8835 	if (!bp)  in bnx2_shutdown()
8840 		dev_close(bp->dev);  in bnx2_shutdown()
8843 		bnx2_set_power_state(bp, PCI_D3hot);  in bnx2_shutdown()