Lines Matching refs:bnx2_write_phy
550 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) in bnx2_write_phy() function
1119 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); in bnx2_5709s_linkup()
1121 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_5709s_linkup()
1393 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_bmsr1()
1402 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_bmsr1()
1419 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_enable_2g5()
1424 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_enable_2g5()
1429 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_enable_2g5()
1445 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_disable_2g5()
1450 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_disable_2g5()
1455 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_disable_2g5()
1473 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1479 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_enable_forced_2g5()
1482 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1502 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_enable_forced_2g5()
1517 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1521 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_disable_forced_2g5()
1524 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1541 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_disable_forced_2g5()
1549 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); in bnx2_5706s_force_link_dn()
1552 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); in bnx2_5706s_force_link_dn()
1554 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); in bnx2_5706s_force_link_dn()
1588 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_set_link()
1625 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_set_link()
1647 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); in bnx2_reset_phy()
1815 bnx2_write_phy(bp, bp->mii_adv, adv & in bnx2_setup_serdes_phy()
1818 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | in bnx2_setup_serdes_phy()
1823 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1826 bnx2_write_phy(bp, bp->mii_adv, adv); in bnx2_setup_serdes_phy()
1827 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1849 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_serdes_phy()
1855 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_serdes_phy()
1856 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | in bnx2_setup_serdes_phy()
2108 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2109 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); in bnx2_setup_copper_phy()
2110 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | in bnx2_setup_copper_phy()
2125 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2142 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_copper_phy()
2151 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_copper_phy()
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); in bnx2_init_5709s_phy()
2199 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); in bnx2_init_5709s_phy()
2201 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); in bnx2_init_5709s_phy()
2210 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); in bnx2_init_5709s_phy()
2212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_init_5709s_phy()
2218 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); in bnx2_init_5709s_phy()
2220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); in bnx2_init_5709s_phy()
2223 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); in bnx2_init_5709s_phy()
2225 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); in bnx2_init_5709s_phy()
2229 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); in bnx2_init_5709s_phy()
2231 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2246 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); in bnx2_init_5708s_phy()
2247 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); in bnx2_init_5708s_phy()
2248 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2252 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); in bnx2_init_5708s_phy()
2256 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); in bnx2_init_5708s_phy()
2261 bnx2_write_phy(bp, BCM5708S_UP1, val); in bnx2_init_5708s_phy()
2268 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2272 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); in bnx2_init_5708s_phy()
2273 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2284 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2286 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); in bnx2_init_5708s_phy()
2287 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2309 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2311 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); in bnx2_init_5706s_phy()
2313 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2315 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); in bnx2_init_5706s_phy()
2320 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2322 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_5706s_phy()
2324 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2326 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); in bnx2_init_5706s_phy()
2341 bnx2_write_phy(bp, 0x18, 0x0c00); in bnx2_init_copper_phy()
2342 bnx2_write_phy(bp, 0x17, 0x000a); in bnx2_init_copper_phy()
2343 bnx2_write_phy(bp, 0x15, 0x310b); in bnx2_init_copper_phy()
2344 bnx2_write_phy(bp, 0x17, 0x201f); in bnx2_init_copper_phy()
2345 bnx2_write_phy(bp, 0x15, 0x9506); in bnx2_init_copper_phy()
2346 bnx2_write_phy(bp, 0x17, 0x401f); in bnx2_init_copper_phy()
2347 bnx2_write_phy(bp, 0x15, 0x14e2); in bnx2_init_copper_phy()
2348 bnx2_write_phy(bp, 0x18, 0x0400); in bnx2_init_copper_phy()
2352 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, in bnx2_init_copper_phy()
2356 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); in bnx2_init_copper_phy()
2361 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2363 bnx2_write_phy(bp, 0x18, val | 0x4000); in bnx2_init_copper_phy()
2366 bnx2_write_phy(bp, 0x10, val | 0x1); in bnx2_init_copper_phy()
2369 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2371 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_copper_phy()
2374 bnx2_write_phy(bp, 0x10, val & ~0x1); in bnx2_init_copper_phy()
2378 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); in bnx2_init_copper_phy()
2386 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); in bnx2_init_copper_phy()
2459 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | in bnx2_set_phy_loopback()
6068 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); in bnx2_5706_serdes_has_link()
6074 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_has_link()
6081 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); in bnx2_5706_serdes_has_link()
6111 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6120 bnx2_write_phy(bp, 0x17, 0x0f01); in bnx2_5706_serdes_timer()
6127 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6137 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_timer()
7187 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_nway_reset()
7201 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); in bnx2_nway_reset()
7892 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()