24 void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val)  in xge_wr_csr()  function
44 	xge_wr_csr(pdata, ENET_CLKEN, 0x3);  in xge_port_reset()
45 	xge_wr_csr(pdata, ENET_SRST, 0xf);  in xge_port_reset()
46 	xge_wr_csr(pdata, ENET_SRST, 0);  in xge_port_reset()
47 	xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 1);  in xge_port_reset()
48 	xge_wr_csr(pdata, CFG_MEM_RAM_SHUTDOWN, 0);  in xge_port_reset()
60 	xge_wr_csr(pdata, ENET_SHIM, DEVM_ARAUX_COH | DEVM_AWAUX_COH);  in xge_port_reset()
69 	xge_wr_csr(pdata, CFG_FORCE_LINK_STATUS_EN, 1);  in xge_traffic_resume()
70 	xge_wr_csr(pdata, FORCE_LINK_STATUS, 1);  in xge_traffic_resume()
72 	xge_wr_csr(pdata, CFG_LINK_AGGR_RESUME, 1);  in xge_traffic_resume()
73 	xge_wr_csr(pdata, RX_DV_GATE_REG, 1);  in xge_traffic_resume()