Lines Matching refs:pdata
127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) in xgbe_get_max_frame() argument
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, in xgbe_usec_to_riwt() argument
140 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, in xgbe_riwt_to_usec() argument
163 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) in xgbe_config_pbl_val() argument
184 pbl = pdata->pbl; in xgbe_config_pbl_val()
186 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
191 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
195 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
199 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) in xgbe_config_osp_mode() argument
211 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
212 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
216 pdata->tx_osp_mode); in xgbe_config_osp_mode()
222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rsf_mode() argument
226 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in xgbe_config_rsf_mode()
232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tsf_mode() argument
236 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in xgbe_config_tsf_mode()
242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, in xgbe_config_rx_threshold() argument
247 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in xgbe_config_rx_threshold()
253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, in xgbe_config_tx_threshold() argument
258 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in xgbe_config_tx_threshold()
264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_rx_coalesce() argument
268 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
269 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
273 pdata->rx_riwt); in xgbe_config_rx_coalesce()
279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_tx_coalesce() argument
284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_buffer_size() argument
288 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
289 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
293 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) in xgbe_config_tso_mode() argument
301 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
302 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); in xgbe_config_tso_mode()
309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) in xgbe_config_sph_mode() argument
313 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
314 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); in xgbe_config_sph_mode()
323 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, in xgbe_write_rss_reg() argument
329 mutex_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
331 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { in xgbe_write_rss_reg()
336 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); in xgbe_write_rss_reg()
338 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); in xgbe_write_rss_reg()
339 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); in xgbe_write_rss_reg()
340 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); in xgbe_write_rss_reg()
341 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); in xgbe_write_rss_reg()
345 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in xgbe_write_rss_reg()
354 mutex_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
359 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) in xgbe_write_rss_hash_key() argument
361 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); in xgbe_write_rss_hash_key()
362 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
366 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, in xgbe_write_rss_hash_key()
375 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) in xgbe_write_rss_lookup_table() argument
380 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
381 ret = xgbe_write_rss_reg(pdata, in xgbe_write_rss_lookup_table()
383 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
391 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) in xgbe_set_rss_hash_key() argument
393 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
395 return xgbe_write_rss_hash_key(pdata); in xgbe_set_rss_hash_key()
398 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, in xgbe_set_rss_lookup_table() argument
403 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
404 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
406 return xgbe_write_rss_lookup_table(pdata); in xgbe_set_rss_lookup_table()
409 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) in xgbe_enable_rss() argument
413 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
417 ret = xgbe_write_rss_hash_key(pdata); in xgbe_enable_rss()
422 ret = xgbe_write_rss_lookup_table(pdata); in xgbe_enable_rss()
427 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
430 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); in xgbe_enable_rss()
435 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) in xgbe_disable_rss() argument
437 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
440 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); in xgbe_disable_rss()
445 static void xgbe_config_rss(struct xgbe_prv_data *pdata) in xgbe_config_rss() argument
449 if (!pdata->hw_feat.rss) in xgbe_config_rss()
452 if (pdata->netdev->features & NETIF_F_RXHASH) in xgbe_config_rss()
453 ret = xgbe_enable_rss(pdata); in xgbe_config_rss()
455 ret = xgbe_disable_rss(pdata); in xgbe_config_rss()
458 netdev_err(pdata->netdev, in xgbe_config_rss()
462 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, in xgbe_is_pfc_queue() argument
469 if (pdata->prio2q_map[prio] != queue) in xgbe_is_pfc_queue()
473 tc = pdata->ets->prio_tc[prio]; in xgbe_is_pfc_queue()
476 if (pdata->pfc->pfc_en & (1 << tc)) in xgbe_is_pfc_queue()
483 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) in xgbe_set_vxlan_id() argument
486 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); in xgbe_set_vxlan_id()
488 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", in xgbe_set_vxlan_id()
489 pdata->vxlan_port); in xgbe_set_vxlan_id()
492 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) in xgbe_enable_vxlan() argument
494 if (!pdata->hw_feat.vxn) in xgbe_enable_vxlan()
498 xgbe_set_vxlan_id(pdata); in xgbe_enable_vxlan()
501 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); in xgbe_enable_vxlan()
504 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); in xgbe_enable_vxlan()
505 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); in xgbe_enable_vxlan()
507 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); in xgbe_enable_vxlan()
510 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) in xgbe_disable_vxlan() argument
512 if (!pdata->hw_feat.vxn) in xgbe_disable_vxlan()
516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); in xgbe_disable_vxlan()
519 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); in xgbe_disable_vxlan()
522 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); in xgbe_disable_vxlan()
524 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); in xgbe_disable_vxlan()
527 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_tx_flow_control() argument
534 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
535 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in xgbe_disable_tx_flow_control()
539 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_disable_tx_flow_control()
542 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_disable_tx_flow_control()
544 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_disable_tx_flow_control()
552 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_tx_flow_control() argument
554 struct ieee_pfc *pfc = pdata->pfc; in xgbe_enable_tx_flow_control()
555 struct ieee_ets *ets = pdata->ets; in xgbe_enable_tx_flow_control()
561 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
564 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
567 if (xgbe_is_pfc_queue(pdata, i)) in xgbe_enable_tx_flow_control()
574 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in xgbe_enable_tx_flow_control()
576 netif_dbg(pdata, drv, pdata->netdev, in xgbe_enable_tx_flow_control()
583 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_enable_tx_flow_control()
586 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_enable_tx_flow_control()
593 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_enable_tx_flow_control()
601 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_rx_flow_control() argument
603 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); in xgbe_disable_rx_flow_control()
608 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_rx_flow_control() argument
610 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); in xgbe_enable_rx_flow_control()
615 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_tx_flow_control() argument
617 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_tx_flow_control()
619 if (pdata->tx_pause || (pfc && pfc->pfc_en)) in xgbe_config_tx_flow_control()
620 xgbe_enable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
622 xgbe_disable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
627 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_rx_flow_control() argument
629 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_rx_flow_control()
631 if (pdata->rx_pause || (pfc && pfc->pfc_en)) in xgbe_config_rx_flow_control()
632 xgbe_enable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
634 xgbe_disable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
639 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_flow_control() argument
641 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_flow_control()
643 xgbe_config_tx_flow_control(pdata); in xgbe_config_flow_control()
644 xgbe_config_rx_flow_control(pdata); in xgbe_config_flow_control()
646 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, in xgbe_config_flow_control()
650 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_dma_interrupts() argument
656 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
657 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, in xgbe_enable_dma_interrupts()
658 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
660 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
662 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
663 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
692 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
704 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
713 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mtl_interrupts() argument
718 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
721 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); in xgbe_enable_mtl_interrupts()
722 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); in xgbe_enable_mtl_interrupts()
725 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); in xgbe_enable_mtl_interrupts()
729 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mac_interrupts() argument
736 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); in xgbe_enable_mac_interrupts()
739 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
740 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
743 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); in xgbe_enable_mac_interrupts()
746 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_ecc_interrupts() argument
750 if (!pdata->vdata->ecc_support) in xgbe_enable_ecc_interrupts()
754 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); in xgbe_enable_ecc_interrupts()
755 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); in xgbe_enable_ecc_interrupts()
765 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_enable_ecc_interrupts()
768 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) in xgbe_disable_ecc_ded() argument
772 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); in xgbe_disable_ecc_ded()
779 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_disable_ecc_ded()
782 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, in xgbe_disable_ecc_sec() argument
787 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); in xgbe_disable_ecc_sec()
802 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_disable_ecc_sec()
805 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) in xgbe_set_speed() argument
823 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) in xgbe_set_speed()
824 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); in xgbe_set_speed()
829 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_stripping() argument
832 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); in xgbe_enable_rx_vlan_stripping()
835 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); in xgbe_enable_rx_vlan_stripping()
838 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); in xgbe_enable_rx_vlan_stripping()
841 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); in xgbe_enable_rx_vlan_stripping()
844 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); in xgbe_enable_rx_vlan_stripping()
849 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_stripping() argument
851 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); in xgbe_disable_rx_vlan_stripping()
856 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_filtering() argument
859 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); in xgbe_enable_rx_vlan_filtering()
862 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); in xgbe_enable_rx_vlan_filtering()
865 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); in xgbe_enable_rx_vlan_filtering()
868 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); in xgbe_enable_rx_vlan_filtering()
876 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); in xgbe_enable_rx_vlan_filtering()
881 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_filtering() argument
884 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); in xgbe_disable_rx_vlan_filtering()
913 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) in xgbe_update_vlan_hash_table() argument
921 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { in xgbe_update_vlan_hash_table()
930 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); in xgbe_update_vlan_hash_table()
935 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, in xgbe_set_promiscuous_mode() argument
940 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) in xgbe_set_promiscuous_mode()
943 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", in xgbe_set_promiscuous_mode()
945 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); in xgbe_set_promiscuous_mode()
949 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
951 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_set_promiscuous_mode()
952 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
958 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, in xgbe_set_all_multicast_mode() argument
963 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) in xgbe_set_all_multicast_mode()
966 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", in xgbe_set_all_multicast_mode()
968 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); in xgbe_set_all_multicast_mode()
973 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, in xgbe_set_mac_reg() argument
992 netif_dbg(pdata, drv, pdata->netdev, in xgbe_set_mac_reg()
999 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); in xgbe_set_mac_reg()
1001 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); in xgbe_set_mac_reg()
1005 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) in xgbe_set_mac_addn_addrs() argument
1007 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_addn_addrs()
1013 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
1016 xgbe_set_promiscuous_mode(pdata, 1); in xgbe_set_mac_addn_addrs()
1019 xgbe_set_mac_reg(pdata, ha, &mac_reg); in xgbe_set_mac_addn_addrs()
1024 xgbe_set_all_multicast_mode(pdata, 1); in xgbe_set_mac_addn_addrs()
1027 xgbe_set_mac_reg(pdata, ha, &mac_reg); in xgbe_set_mac_addn_addrs()
1035 xgbe_set_mac_reg(pdata, NULL, &mac_reg); in xgbe_set_mac_addn_addrs()
1038 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) in xgbe_set_mac_hash_table() argument
1040 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_hash_table()
1048 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); in xgbe_set_mac_hash_table()
1049 hash_table_count = pdata->hw_feat.hash_table_size / 32; in xgbe_set_mac_hash_table()
1068 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); in xgbe_set_mac_hash_table()
1073 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) in xgbe_add_mac_addresses() argument
1075 if (pdata->hw_feat.hash_table_size) in xgbe_add_mac_addresses()
1076 xgbe_set_mac_hash_table(pdata); in xgbe_add_mac_addresses()
1078 xgbe_set_mac_addn_addrs(pdata); in xgbe_add_mac_addresses()
1083 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) in xgbe_set_mac_address() argument
1091 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); in xgbe_set_mac_address()
1092 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); in xgbe_set_mac_address()
1097 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) in xgbe_config_rx_mode() argument
1099 struct net_device *netdev = pdata->netdev; in xgbe_config_rx_mode()
1105 xgbe_set_promiscuous_mode(pdata, pr_mode); in xgbe_config_rx_mode()
1106 xgbe_set_all_multicast_mode(pdata, am_mode); in xgbe_config_rx_mode()
1108 xgbe_add_mac_addresses(pdata); in xgbe_config_rx_mode()
1113 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_clr_gpio() argument
1120 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_clr_gpio()
1123 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_clr_gpio()
1128 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_set_gpio() argument
1135 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_set_gpio()
1138 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_set_gpio()
1143 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v2() argument
1153 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v2()
1165 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_read_mmd_regs_v2()
1166 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_read_mmd_regs_v2()
1168 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1169 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1170 mmd_data = XPCS16_IOREAD(pdata, offset); in xgbe_read_mmd_regs_v2()
1171 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1176 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v2() argument
1185 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v2()
1197 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_write_mmd_regs_v2()
1198 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_write_mmd_regs_v2()
1200 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1201 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1202 XPCS16_IOWRITE(pdata, offset, mmd_data); in xgbe_write_mmd_regs_v2()
1203 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1206 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v1() argument
1216 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v1()
1227 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1228 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_read_mmd_regs_v1()
1229 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); in xgbe_read_mmd_regs_v1()
1230 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1235 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v1() argument
1244 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v1()
1255 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1256 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_write_mmd_regs_v1()
1257 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); in xgbe_write_mmd_regs_v1()
1258 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1261 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs() argument
1264 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1266 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1270 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1274 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs() argument
1277 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1279 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1283 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1287 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, in xgbe_write_ext_mii_regs() argument
1292 reinit_completion(&pdata->mdio_complete); in xgbe_write_ext_mii_regs()
1297 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_write_ext_mii_regs()
1303 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_write_ext_mii_regs()
1305 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_write_ext_mii_regs()
1306 netdev_err(pdata->netdev, "mdio write operation timed out\n"); in xgbe_write_ext_mii_regs()
1313 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, int addr, in xgbe_read_ext_mii_regs() argument
1318 reinit_completion(&pdata->mdio_complete); in xgbe_read_ext_mii_regs()
1323 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_read_ext_mii_regs()
1328 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_read_ext_mii_regs()
1330 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_read_ext_mii_regs()
1331 netdev_err(pdata->netdev, "mdio read operation timed out\n"); in xgbe_read_ext_mii_regs()
1335 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); in xgbe_read_ext_mii_regs()
1338 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, in xgbe_set_ext_mii_mode() argument
1341 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); in xgbe_set_ext_mii_mode()
1355 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in xgbe_set_ext_mii_mode()
1365 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_disable_rx_csum() argument
1367 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); in xgbe_disable_rx_csum()
1372 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_enable_rx_csum() argument
1374 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); in xgbe_enable_rx_csum()
1428 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, in xgbe_rx_desc_reset() argument
1432 unsigned int rx_usecs = pdata->rx_usecs; in xgbe_rx_desc_reset()
1433 unsigned int rx_frames = pdata->rx_frames; in xgbe_rx_desc_reset()
1478 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_rx_desc_init() local
1491 xgbe_rx_desc_reset(pdata, rdata, i); in xgbe_rx_desc_init()
1512 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, in xgbe_update_tstamp_addend() argument
1518 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); in xgbe_update_tstamp_addend()
1519 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); in xgbe_update_tstamp_addend()
1522 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) in xgbe_update_tstamp_addend()
1526 netdev_err(pdata->netdev, in xgbe_update_tstamp_addend()
1530 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, in xgbe_set_tstamp_time() argument
1536 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); in xgbe_set_tstamp_time()
1537 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); in xgbe_set_tstamp_time()
1538 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); in xgbe_set_tstamp_time()
1541 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) in xgbe_set_tstamp_time()
1545 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); in xgbe_set_tstamp_time()
1548 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) in xgbe_get_tstamp_time() argument
1552 nsec = XGMAC_IOREAD(pdata, MAC_STSR); in xgbe_get_tstamp_time()
1554 nsec += XGMAC_IOREAD(pdata, MAC_STNR); in xgbe_get_tstamp_time()
1559 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) in xgbe_get_tx_tstamp() argument
1564 if (pdata->vdata->tx_tstamp_workaround) { in xgbe_get_tx_tstamp()
1565 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); in xgbe_get_tx_tstamp()
1566 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); in xgbe_get_tx_tstamp()
1568 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); in xgbe_get_tx_tstamp()
1569 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); in xgbe_get_tx_tstamp()
1600 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, in xgbe_config_tstamp() argument
1612 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); in xgbe_config_tstamp()
1619 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); in xgbe_config_tstamp()
1620 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); in xgbe_config_tstamp()
1621 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); in xgbe_config_tstamp()
1622 xgbe_set_tstamp_time(pdata, 0, 0); in xgbe_config_tstamp()
1625 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, in xgbe_config_tstamp()
1634 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_tx_start_xmit() local
1647 if (pdata->tx_usecs && !channel->tx_timer_active) { in xgbe_tx_start_xmit()
1650 jiffies + usecs_to_jiffies(pdata->tx_usecs)); in xgbe_tx_start_xmit()
1658 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_xmit() local
1706 if (!pdata->tx_frames) in xgbe_dev_xmit()
1708 else if (tx_packets > pdata->tx_frames) in xgbe_dev_xmit()
1710 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) in xgbe_dev_xmit()
1721 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1741 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1800 pdata->ext_stats.tx_tso_packets += tx_packets; in xgbe_dev_xmit()
1819 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; in xgbe_dev_xmit()
1858 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; in xgbe_dev_xmit()
1859 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; in xgbe_dev_xmit()
1872 if (netif_msg_tx_queued(pdata)) in xgbe_dev_xmit()
1873 xgbe_dump_tx_desc(pdata, ring, start_index, in xgbe_dev_xmit()
1881 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, in xgbe_dev_xmit()
1896 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read() local
1901 struct net_device *netdev = pdata->netdev; in xgbe_dev_read()
1916 if (netif_msg_rx_status(pdata)) in xgbe_dev_read()
1917 xgbe_dump_rx_desc(pdata, ring, ring->cur); in xgbe_dev_read()
1945 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
1994 pdata->ext_stats.rx_vxlan_packets++; in xgbe_dev_read()
2009 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); in xgbe_dev_read()
2020 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", in xgbe_dev_read()
2032 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
2038 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
2045 pdata->ext_stats.rxq_packets[channel->queue_index]++; in xgbe_dev_read()
2046 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; in xgbe_dev_read()
2149 static int __xgbe_exit(struct xgbe_prv_data *pdata) in __xgbe_exit() argument
2156 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); in __xgbe_exit()
2160 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
2171 static int xgbe_exit(struct xgbe_prv_data *pdata) in xgbe_exit() argument
2178 ret = __xgbe_exit(pdata); in xgbe_exit()
2182 return __xgbe_exit(pdata); in xgbe_exit()
2185 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) in xgbe_flush_tx_queues() argument
2189 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
2192 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
2193 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in xgbe_flush_tx_queues()
2196 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
2198 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
2209 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) in xgbe_config_dma_bus() argument
2213 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); in xgbe_config_dma_bus()
2220 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
2221 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
2222 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
2223 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
2225 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); in xgbe_config_dma_bus()
2228 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
2229 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, in xgbe_config_dma_bus()
2230 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
2232 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
2233 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, in xgbe_config_dma_bus()
2234 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
2237 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) in xgbe_config_dma_cache() argument
2239 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
2240 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
2241 if (pdata->awarcr) in xgbe_config_dma_cache()
2242 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
2245 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) in xgbe_config_mtl_mode() argument
2250 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); in xgbe_config_mtl_mode()
2253 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
2254 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_mtl_mode()
2256 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); in xgbe_config_mtl_mode()
2260 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); in xgbe_config_mtl_mode()
2263 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_queue_flow_control_threshold() argument
2270 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_queue_flow_control_threshold()
2272 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { in xgbe_queue_flow_control_threshold()
2274 rfa = pdata->pfc_rfa; in xgbe_queue_flow_control_threshold()
2288 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
2289 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
2295 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
2296 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
2302 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
2303 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
2324 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
2325 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
2328 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_calculate_flow_control_threshold() argument
2334 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
2337 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); in xgbe_calculate_flow_control_threshold()
2341 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) in xgbe_config_flow_control_threshold() argument
2345 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
2346 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, in xgbe_config_flow_control_threshold()
2347 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
2348 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, in xgbe_config_flow_control_threshold()
2349 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
2353 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_tx_fifo_size() argument
2356 return min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
2357 pdata->hw_feat.tx_fifo_size); in xgbe_get_tx_fifo_size()
2360 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_rx_fifo_size() argument
2363 return min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
2364 pdata->hw_feat.rx_fifo_size); in xgbe_get_rx_fifo_size()
2413 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) in xgbe_get_pfc_delay() argument
2418 if (pdata->pfc->delay) in xgbe_get_pfc_delay()
2419 return pdata->pfc->delay / 8; in xgbe_get_pfc_delay()
2422 delay = xgbe_get_max_frame(pdata); in xgbe_get_pfc_delay()
2437 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) in xgbe_get_pfc_queues() argument
2442 if (!pdata->pfc->pfc_en) in xgbe_get_pfc_queues()
2446 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_get_pfc_queues()
2448 if (!xgbe_is_pfc_queue(pdata, i)) in xgbe_get_pfc_queues()
2451 pdata->pfcq[i] = 1; in xgbe_get_pfc_queues()
2458 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, in xgbe_calculate_dcb_fifo() argument
2467 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_calculate_dcb_fifo()
2468 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_calculate_dcb_fifo()
2469 pfc_count = xgbe_get_pfc_queues(pdata); in xgbe_calculate_dcb_fifo()
2483 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); in xgbe_calculate_dcb_fifo()
2484 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); in xgbe_calculate_dcb_fifo()
2486 if (pdata->pfc_rfa > q_fifo_size) { in xgbe_calculate_dcb_fifo()
2487 addn_fifo = pdata->pfc_rfa - q_fifo_size; in xgbe_calculate_dcb_fifo()
2504 if (!pdata->pfcq[i] || !addn_fifo) in xgbe_calculate_dcb_fifo()
2508 netdev_warn(pdata->netdev, in xgbe_calculate_dcb_fifo()
2529 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_tx_fifo_size() argument
2535 fifo_size = xgbe_get_tx_fifo_size(pdata); in xgbe_config_tx_fifo_size()
2537 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
2539 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_fifo_size()
2540 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); in xgbe_config_tx_fifo_size()
2542 netif_info(pdata, drv, pdata->netdev, in xgbe_config_tx_fifo_size()
2544 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
2547 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_fifo_size() argument
2555 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); in xgbe_config_rx_fifo_size()
2556 pdata->pfc_rfa = 0; in xgbe_config_rx_fifo_size()
2558 fifo_size = xgbe_get_rx_fifo_size(pdata); in xgbe_config_rx_fifo_size()
2559 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2562 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
2564 if (pdata->pfc && pdata->ets) in xgbe_config_rx_fifo_size()
2565 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); in xgbe_config_rx_fifo_size()
2569 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2570 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); in xgbe_config_rx_fifo_size()
2572 xgbe_calculate_flow_control_threshold(pdata, fifo); in xgbe_config_rx_fifo_size()
2573 xgbe_config_flow_control_threshold(pdata); in xgbe_config_rx_fifo_size()
2575 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { in xgbe_config_rx_fifo_size()
2576 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2577 "%u Rx hardware queues\n", pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2578 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2579 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2583 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2585 pdata->rx_q_count, in xgbe_config_rx_fifo_size()
2590 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) in xgbe_config_queue_mapping() argument
2601 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2602 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2604 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
2606 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2608 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2610 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2614 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2616 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2618 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2623 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
2632 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2635 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2639 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2642 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2650 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2658 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2661 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2664 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2671 static void xgbe_config_tc(struct xgbe_prv_data *pdata) in xgbe_config_tc() argument
2676 netdev_reset_tc(pdata->netdev); in xgbe_config_tc()
2677 if (!pdata->num_tcs) in xgbe_config_tc()
2680 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); in xgbe_config_tc()
2682 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { in xgbe_config_tc()
2683 while ((queue < pdata->tx_q_count) && in xgbe_config_tc()
2684 (pdata->q2tc_map[queue] == i)) in xgbe_config_tc()
2687 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", in xgbe_config_tc()
2689 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); in xgbe_config_tc()
2693 if (!pdata->ets) in xgbe_config_tc()
2697 netdev_set_prio_tc_map(pdata->netdev, prio, in xgbe_config_tc()
2698 pdata->ets->prio_tc[prio]); in xgbe_config_tc()
2701 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) in xgbe_config_dcb_tc() argument
2703 struct ieee_ets *ets = pdata->ets; in xgbe_config_dcb_tc()
2714 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); in xgbe_config_dcb_tc()
2717 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; in xgbe_config_dcb_tc()
2722 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_dcb_tc()
2731 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", in xgbe_config_dcb_tc()
2734 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_config_dcb_tc()
2739 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_dcb_tc()
2744 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2746 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_dcb_tc()
2753 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2755 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_dcb_tc()
2757 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, in xgbe_config_dcb_tc()
2763 xgbe_config_tc(pdata); in xgbe_config_dcb_tc()
2766 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) in xgbe_config_dcb_pfc() argument
2768 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2770 netif_tx_stop_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2773 pdata->hw_if.disable_rx(pdata); in xgbe_config_dcb_pfc()
2776 xgbe_config_rx_fifo_size(pdata); in xgbe_config_dcb_pfc()
2777 xgbe_config_flow_control(pdata); in xgbe_config_dcb_pfc()
2779 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2781 pdata->hw_if.enable_rx(pdata); in xgbe_config_dcb_pfc()
2784 netif_tx_start_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2788 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) in xgbe_config_mac_address() argument
2790 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); in xgbe_config_mac_address()
2793 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2794 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); in xgbe_config_mac_address()
2795 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); in xgbe_config_mac_address()
2796 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); in xgbe_config_mac_address()
2800 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) in xgbe_config_jumbo_enable() argument
2804 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; in xgbe_config_jumbo_enable()
2806 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); in xgbe_config_jumbo_enable()
2809 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) in xgbe_config_mac_speed() argument
2811 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2814 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) in xgbe_config_checksum_offload() argument
2816 if (pdata->netdev->features & NETIF_F_RXCSUM) in xgbe_config_checksum_offload()
2817 xgbe_enable_rx_csum(pdata); in xgbe_config_checksum_offload()
2819 xgbe_disable_rx_csum(pdata); in xgbe_config_checksum_offload()
2822 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) in xgbe_config_vlan_support() argument
2825 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); in xgbe_config_vlan_support()
2826 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); in xgbe_config_vlan_support()
2829 xgbe_update_vlan_hash_table(pdata); in xgbe_config_vlan_support()
2831 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_config_vlan_support()
2832 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2834 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2836 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) in xgbe_config_vlan_support()
2837 xgbe_enable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2839 xgbe_disable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2842 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) in xgbe_mmc_read() argument
2847 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2876 val = XGMAC_IOREAD(pdata, reg_lo); in xgbe_mmc_read()
2879 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); in xgbe_mmc_read()
2884 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_tx_mmc_int() argument
2886 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2887 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); in xgbe_tx_mmc_int()
2891 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_tx_mmc_int()
2895 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_tx_mmc_int()
2899 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2903 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2907 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_tx_mmc_int()
2911 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_tx_mmc_int()
2915 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_tx_mmc_int()
2919 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_tx_mmc_int()
2923 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_tx_mmc_int()
2927 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_tx_mmc_int()
2931 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2935 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2939 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
2943 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_tx_mmc_int()
2947 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_tx_mmc_int()
2951 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_tx_mmc_int()
2955 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_tx_mmc_int()
2959 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_tx_mmc_int()
2962 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_rx_mmc_int() argument
2964 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
2965 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); in xgbe_rx_mmc_int()
2969 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_rx_mmc_int()
2973 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_rx_mmc_int()
2977 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_rx_mmc_int()
2981 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2985 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
2989 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_rx_mmc_int()
2993 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_rx_mmc_int()
2997 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_rx_mmc_int()
3001 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_rx_mmc_int()
3005 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_rx_mmc_int()
3009 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_rx_mmc_int()
3013 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_rx_mmc_int()
3017 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_rx_mmc_int()
3021 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_rx_mmc_int()
3025 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_rx_mmc_int()
3029 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_rx_mmc_int()
3033 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
3037 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_rx_mmc_int()
3041 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_rx_mmc_int()
3045 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_rx_mmc_int()
3049 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_rx_mmc_int()
3053 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_rx_mmc_int()
3057 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_rx_mmc_int()
3060 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) in xgbe_read_mmc_stats() argument
3062 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
3065 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); in xgbe_read_mmc_stats()
3068 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
3071 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
3074 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3077 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3080 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
3083 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
3086 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
3089 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
3092 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
3095 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
3098 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3101 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3104 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3107 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_read_mmc_stats()
3110 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
3113 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_read_mmc_stats()
3116 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
3119 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_read_mmc_stats()
3122 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
3125 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
3128 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
3131 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3134 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3137 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_read_mmc_stats()
3140 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_read_mmc_stats()
3143 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_read_mmc_stats()
3146 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_read_mmc_stats()
3149 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_read_mmc_stats()
3152 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
3155 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
3158 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
3161 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
3164 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
3167 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
3170 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3173 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_read_mmc_stats()
3176 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_read_mmc_stats()
3179 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
3182 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_read_mmc_stats()
3185 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_read_mmc_stats()
3188 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_read_mmc_stats()
3191 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); in xgbe_read_mmc_stats()
3194 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) in xgbe_config_mmc() argument
3197 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
3200 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); in xgbe_config_mmc()
3203 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, in xgbe_txq_prepare_tx_stop() argument
3215 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); in xgbe_txq_prepare_tx_stop()
3224 netdev_info(pdata->netdev, in xgbe_txq_prepare_tx_stop()
3229 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, in xgbe_prepare_tx_stop() argument
3236 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
3237 return xgbe_txq_prepare_tx_stop(pdata, queue); in xgbe_prepare_tx_stop()
3257 tx_status = XGMAC_IOREAD(pdata, tx_dsr); in xgbe_prepare_tx_stop()
3267 netdev_info(pdata->netdev, in xgbe_prepare_tx_stop()
3272 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) in xgbe_enable_tx() argument
3277 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
3278 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
3281 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
3285 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
3286 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, in xgbe_enable_tx()
3290 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_enable_tx()
3293 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) in xgbe_disable_tx() argument
3298 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3299 xgbe_prepare_tx_stop(pdata, i); in xgbe_disable_tx()
3302 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_disable_tx()
3305 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3306 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); in xgbe_disable_tx()
3309 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
3310 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
3313 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
3317 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, in xgbe_prepare_rx_stop() argument
3329 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); in xgbe_prepare_rx_stop()
3338 netdev_info(pdata->netdev, in xgbe_prepare_rx_stop()
3343 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) in xgbe_enable_rx() argument
3348 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
3349 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
3352 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
3357 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
3359 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); in xgbe_enable_rx()
3362 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); in xgbe_enable_rx()
3363 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); in xgbe_enable_rx()
3364 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); in xgbe_enable_rx()
3365 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); in xgbe_enable_rx()
3368 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) in xgbe_disable_rx() argument
3373 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); in xgbe_disable_rx()
3374 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); in xgbe_disable_rx()
3375 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); in xgbe_disable_rx()
3376 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); in xgbe_disable_rx()
3379 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
3380 xgbe_prepare_rx_stop(pdata, i); in xgbe_disable_rx()
3383 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); in xgbe_disable_rx()
3386 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
3387 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
3390 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
3394 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) in xgbe_powerup_tx() argument
3399 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
3400 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
3403 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
3407 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_powerup_tx()
3410 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) in xgbe_powerdown_tx() argument
3415 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
3416 xgbe_prepare_tx_stop(pdata, i); in xgbe_powerdown_tx()
3419 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_powerdown_tx()
3422 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
3423 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
3426 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
3430 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) in xgbe_powerup_rx() argument
3435 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
3436 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
3439 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
3443 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) in xgbe_powerdown_rx() argument
3448 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
3449 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
3452 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
3456 static int xgbe_init(struct xgbe_prv_data *pdata) in xgbe_init() argument
3458 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
3464 ret = xgbe_flush_tx_queues(pdata); in xgbe_init()
3466 netdev_err(pdata->netdev, "error flushing TX queues\n"); in xgbe_init()
3473 xgbe_config_dma_bus(pdata); in xgbe_init()
3474 xgbe_config_dma_cache(pdata); in xgbe_init()
3475 xgbe_config_osp_mode(pdata); in xgbe_init()
3476 xgbe_config_pbl_val(pdata); in xgbe_init()
3477 xgbe_config_rx_coalesce(pdata); in xgbe_init()
3478 xgbe_config_tx_coalesce(pdata); in xgbe_init()
3479 xgbe_config_rx_buffer_size(pdata); in xgbe_init()
3480 xgbe_config_tso_mode(pdata); in xgbe_init()
3481 xgbe_config_sph_mode(pdata); in xgbe_init()
3482 xgbe_config_rss(pdata); in xgbe_init()
3483 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
3484 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
3485 xgbe_enable_dma_interrupts(pdata); in xgbe_init()
3490 xgbe_config_mtl_mode(pdata); in xgbe_init()
3491 xgbe_config_queue_mapping(pdata); in xgbe_init()
3492 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
3493 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
3494 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
3495 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
3496 xgbe_config_tx_fifo_size(pdata); in xgbe_init()
3497 xgbe_config_rx_fifo_size(pdata); in xgbe_init()
3501 xgbe_config_dcb_tc(pdata); in xgbe_init()
3502 xgbe_enable_mtl_interrupts(pdata); in xgbe_init()
3507 xgbe_config_mac_address(pdata); in xgbe_init()
3508 xgbe_config_rx_mode(pdata); in xgbe_init()
3509 xgbe_config_jumbo_enable(pdata); in xgbe_init()
3510 xgbe_config_flow_control(pdata); in xgbe_init()
3511 xgbe_config_mac_speed(pdata); in xgbe_init()
3512 xgbe_config_checksum_offload(pdata); in xgbe_init()
3513 xgbe_config_vlan_support(pdata); in xgbe_init()
3514 xgbe_config_mmc(pdata); in xgbe_init()
3515 xgbe_enable_mac_interrupts(pdata); in xgbe_init()
3520 xgbe_enable_ecc_interrupts(pdata); in xgbe_init()