285 	volatile unsigned short rdp;	/* register data port */  member
313 	writereg(&ll->rdp, (leptr & 0xFFFF));  in load_csrs()
315 	writereg(&ll->rdp, leptr >> 16);  in load_csrs()
317 	writereg(&ll->rdp, lp->busmaster_regval);  in load_csrs()
532 	writereg(&ll->rdp, LE_C0_INIT);  in init_restart_lance()
535 	for (i = 0; (i < 100) && !(ll->rdp & LE_C0_IDON); i++) {  in init_restart_lance()
538 	if ((i == 100) || (ll->rdp & LE_C0_ERR)) {  in init_restart_lance()
540 		       i, ll->rdp);  in init_restart_lance()
543 	if ((ll->rdp & LE_C0_ERR)) {  in init_restart_lance()
545 		       i, ll->rdp);  in init_restart_lance()
548 	writereg(&ll->rdp, LE_C0_IDON);  in init_restart_lance()
549 	writereg(&ll->rdp, LE_C0_STRT);  in init_restart_lance()
550 	writereg(&ll->rdp, LE_C0_INEA);  in init_restart_lance()
675 				writereg(&ll->rdp, LE_C0_STOP);  in lance_tx()
691 				writereg(&ll->rdp, LE_C0_STOP);  in lance_tx()
741 	csr0 = ll->rdp;  in lance_interrupt()
744 	writereg(&ll->rdp, csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT));  in lance_interrupt()
748 		writereg(&ll->rdp, LE_C0_BABL | LE_C0_ERR | LE_C0_MISS |  in lance_interrupt()
766 		writereg(&ll->rdp, LE_C0_STOP);  in lance_interrupt()
774 	writereg(&ll->rdp, LE_C0_INEA);  in lance_interrupt()
775 	writereg(&ll->rdp, LE_C0_INEA);  in lance_interrupt()
788 	writereg(&ll->rdp, LE_C0_STOP);  in lance_open()
848 	writereg(&ll->rdp, LE_C0_STOP);  in lance_close()
877 	writereg(&ll->rdp, LE_C0_STOP);  in lance_reset()
892 		dev->name, ll->rdp);  in lance_tx_timeout()
933 	writereg(&ll->rdp, LE_C0_INEA | LE_C0_TDMD);  in lance_start_xmit()
989 	writereg(&ll->rdp, LE_C0_STOP);  in lance_set_multicast()