Lines Matching refs:ena_dev
95 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, in ena_com_mem_addr_set() argument
99 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { in ena_com_mem_addr_set()
327 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, in ena_com_init_io_sq() argument
336 io_sq->dma_addr_bits = ena_dev->dma_addr_bits; in ena_com_init_io_sq()
345 dev_node = dev_to_node(ena_dev->dmadev); in ena_com_init_io_sq()
346 set_dev_node(ena_dev->dmadev, ctx->numa_node); in ena_com_init_io_sq()
348 dma_zalloc_coherent(ena_dev->dmadev, size, in ena_com_init_io_sq()
351 set_dev_node(ena_dev->dmadev, dev_node); in ena_com_init_io_sq()
354 dma_zalloc_coherent(ena_dev->dmadev, size, in ena_com_init_io_sq()
359 dev_node = dev_to_node(ena_dev->dmadev); in ena_com_init_io_sq()
360 set_dev_node(ena_dev->dmadev, ctx->numa_node); in ena_com_init_io_sq()
362 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); in ena_com_init_io_sq()
363 set_dev_node(ena_dev->dmadev, dev_node); in ena_com_init_io_sq()
366 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); in ena_com_init_io_sq()
382 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, in ena_com_init_io_cq() argument
399 prev_node = dev_to_node(ena_dev->dmadev); in ena_com_init_io_cq()
400 set_dev_node(ena_dev->dmadev, ctx->numa_node); in ena_com_init_io_cq()
402 dma_zalloc_coherent(ena_dev->dmadev, size, in ena_com_init_io_cq()
404 set_dev_node(ena_dev->dmadev, prev_node); in ena_com_init_io_cq()
407 dma_zalloc_coherent(ena_dev->dmadev, size, in ena_com_init_io_cq()
603 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) in ena_com_reg_bar_read32() argument
605 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_reg_bar_read32()
619 return readl(ena_dev->reg_bar + offset); in ena_com_reg_bar_read32()
630 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); in ena_com_reg_bar_read32()
677 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, in ena_com_destroy_io_sq() argument
680 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_destroy_io_sq()
712 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, in ena_com_io_queue_free() argument
721 dma_free_coherent(ena_dev->dmadev, size, in ena_com_io_queue_free()
732 dma_free_coherent(ena_dev->dmadev, size, in ena_com_io_queue_free()
736 devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr); in ena_com_io_queue_free()
742 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, in wait_for_reset_state() argument
751 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); in wait_for_reset_state()
768 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, in ena_com_check_supported_feature_id() argument
775 !(ena_dev->supported_features & feature_mask)) in ena_com_check_supported_feature_id()
781 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, in ena_com_get_feature_ex() argument
791 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { in ena_com_get_feature_ex()
797 admin_queue = &ena_dev->admin_queue; in ena_com_get_feature_ex()
807 ret = ena_com_mem_addr_set(ena_dev, in ena_com_get_feature_ex()
834 static int ena_com_get_feature(struct ena_com_dev *ena_dev, in ena_com_get_feature() argument
838 return ena_com_get_feature_ex(ena_dev, in ena_com_get_feature()
845 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) in ena_com_hash_key_allocate() argument
847 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_key_allocate()
850 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), in ena_com_hash_key_allocate()
859 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) in ena_com_hash_key_destroy() argument
861 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_key_destroy()
864 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), in ena_com_hash_key_destroy()
869 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) in ena_com_hash_ctrl_init() argument
871 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_ctrl_init()
874 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), in ena_com_hash_ctrl_init()
883 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) in ena_com_hash_ctrl_destroy() argument
885 struct ena_rss *rss = &ena_dev->rss; in ena_com_hash_ctrl_destroy()
888 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), in ena_com_hash_ctrl_destroy()
893 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, in ena_com_indirect_table_allocate() argument
896 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_allocate()
901 ret = ena_com_get_feature(ena_dev, &get_resp, in ena_com_indirect_table_allocate()
918 dma_zalloc_coherent(ena_dev->dmadev, tbl_size, in ena_com_indirect_table_allocate()
925 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); in ena_com_indirect_table_allocate()
937 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, in ena_com_indirect_table_allocate()
945 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) in ena_com_indirect_table_destroy() argument
947 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_destroy()
952 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, in ena_com_indirect_table_destroy()
957 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); in ena_com_indirect_table_destroy()
961 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, in ena_com_create_io_sq() argument
964 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_create_io_sq()
997 ret = ena_com_mem_addr_set(ena_dev, in ena_com_create_io_sq()
1018 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_sq()
1022 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar in ena_com_create_io_sq()
1026 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + in ena_com_create_io_sq()
1035 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) in ena_com_ind_tbl_convert_to_device() argument
1037 struct ena_rss *rss = &ena_dev->rss; in ena_com_ind_tbl_convert_to_device()
1047 io_sq = &ena_dev->io_sq_queues[qid]; in ena_com_ind_tbl_convert_to_device()
1058 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev) in ena_com_ind_tbl_convert_from_device() argument
1061 struct ena_rss *rss = &ena_dev->rss; in ena_com_ind_tbl_convert_from_device()
1066 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i; in ena_com_ind_tbl_convert_from_device()
1082 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) in ena_com_init_interrupt_moderation_table() argument
1088 ena_dev->intr_moder_tbl = in ena_com_init_interrupt_moderation_table()
1089 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); in ena_com_init_interrupt_moderation_table()
1090 if (!ena_dev->intr_moder_tbl) in ena_com_init_interrupt_moderation_table()
1093 ena_com_config_default_interrupt_moderation_table(ena_dev); in ena_com_init_interrupt_moderation_table()
1098 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, in ena_com_update_intr_delay_resolution() argument
1101 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; in ena_com_update_intr_delay_resolution()
1108 ena_dev->intr_delay_resolution = intr_delay_resolution; in ena_com_update_intr_delay_resolution()
1115 ena_dev->intr_moder_tx_interval /= intr_delay_resolution; in ena_com_update_intr_delay_resolution()
1154 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, in ena_com_create_io_cq() argument
1157 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_create_io_cq()
1174 ret = ena_com_mem_addr_set(ena_dev, in ena_com_create_io_cq()
1194 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_cq()
1199 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_cq()
1204 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_create_io_cq()
1212 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, in ena_com_get_io_handlers() argument
1222 *io_sq = &ena_dev->io_sq_queues[qid]; in ena_com_get_io_handlers()
1223 *io_cq = &ena_dev->io_cq_queues[qid]; in ena_com_get_io_handlers()
1228 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) in ena_com_abort_admin_commands() argument
1230 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_abort_admin_commands()
1248 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) in ena_com_wait_for_abort_completion() argument
1250 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_wait_for_abort_completion()
1262 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, in ena_com_destroy_io_cq() argument
1265 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_destroy_io_cq()
1287 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) in ena_com_get_admin_running_state() argument
1289 return ena_dev->admin_queue.running_state; in ena_com_get_admin_running_state()
1292 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) in ena_com_set_admin_running_state() argument
1294 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_set_admin_running_state()
1298 ena_dev->admin_queue.running_state = state; in ena_com_set_admin_running_state()
1302 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) in ena_com_admin_aenq_enable() argument
1304 u16 depth = ena_dev->aenq.q_depth; in ena_com_admin_aenq_enable()
1306 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); in ena_com_admin_aenq_enable()
1311 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); in ena_com_admin_aenq_enable()
1314 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) in ena_com_set_aenq_config() argument
1322 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG); in ena_com_set_aenq_config()
1335 admin_queue = &ena_dev->admin_queue; in ena_com_set_aenq_config()
1354 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) in ena_com_get_dma_width() argument
1356 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); in ena_com_get_dma_width()
1374 ena_dev->dma_addr_bits = width; in ena_com_get_dma_width()
1379 int ena_com_validate_version(struct ena_com_dev *ena_dev) in ena_com_validate_version() argument
1388 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); in ena_com_validate_version()
1389 ctrl_ver = ena_com_reg_bar_read32(ena_dev, in ena_com_validate_version()
1431 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) in ena_com_admin_destroy() argument
1433 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_admin_destroy()
1436 struct ena_com_aenq *aenq = &ena_dev->aenq; in ena_com_admin_destroy()
1440 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); in ena_com_admin_destroy()
1444 dma_free_coherent(ena_dev->dmadev, size, sq->entries, in ena_com_admin_destroy()
1450 dma_free_coherent(ena_dev->dmadev, size, cq->entries, in ena_com_admin_destroy()
1455 if (ena_dev->aenq.entries) in ena_com_admin_destroy()
1456 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, in ena_com_admin_destroy()
1461 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) in ena_com_set_admin_polling_mode() argument
1468 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); in ena_com_set_admin_polling_mode()
1469 ena_dev->admin_queue.polling = polling; in ena_com_set_admin_polling_mode()
1472 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) in ena_com_mmio_reg_read_request_init() argument
1474 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_mmio_reg_read_request_init()
1478 dma_zalloc_coherent(ena_dev->dmadev, in ena_com_mmio_reg_read_request_init()
1484 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); in ena_com_mmio_reg_read_request_init()
1493 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) in ena_com_set_mmio_read_mode() argument
1495 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_set_mmio_read_mode()
1500 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) in ena_com_mmio_reg_read_request_destroy() argument
1502 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_mmio_reg_read_request_destroy()
1504 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); in ena_com_mmio_reg_read_request_destroy()
1505 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); in ena_com_mmio_reg_read_request_destroy()
1507 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), in ena_com_mmio_reg_read_request_destroy()
1513 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) in ena_com_mmio_reg_read_request_write_dev_addr() argument
1515 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; in ena_com_mmio_reg_read_request_write_dev_addr()
1521 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); in ena_com_mmio_reg_read_request_write_dev_addr()
1522 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); in ena_com_mmio_reg_read_request_write_dev_addr()
1525 int ena_com_admin_init(struct ena_com_dev *ena_dev, in ena_com_admin_init() argument
1529 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_admin_init()
1533 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); in ena_com_admin_init()
1547 admin_queue->q_dmadev = ena_dev->dmadev; in ena_com_admin_init()
1568 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + in ena_com_admin_init()
1574 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); in ena_com_admin_init()
1575 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); in ena_com_admin_init()
1580 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); in ena_com_admin_init()
1581 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); in ena_com_admin_init()
1595 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); in ena_com_admin_init()
1596 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); in ena_com_admin_init()
1597 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); in ena_com_admin_init()
1605 ena_com_admin_destroy(ena_dev); in ena_com_admin_init()
1610 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, in ena_com_create_io_queue() argument
1623 io_sq = &ena_dev->io_sq_queues[ctx->qid]; in ena_com_create_io_queue()
1624 io_cq = &ena_dev->io_cq_queues[ctx->qid]; in ena_com_create_io_queue()
1645 min_t(u32, ena_dev->tx_max_header_size, SZ_256); in ena_com_create_io_queue()
1647 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); in ena_com_create_io_queue()
1650 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); in ena_com_create_io_queue()
1654 ret = ena_com_create_io_cq(ena_dev, io_cq); in ena_com_create_io_queue()
1658 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); in ena_com_create_io_queue()
1665 ena_com_destroy_io_cq(ena_dev, io_cq); in ena_com_create_io_queue()
1667 ena_com_io_queue_free(ena_dev, io_sq, io_cq); in ena_com_create_io_queue()
1671 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) in ena_com_destroy_io_queue() argument
1682 io_sq = &ena_dev->io_sq_queues[qid]; in ena_com_destroy_io_queue()
1683 io_cq = &ena_dev->io_cq_queues[qid]; in ena_com_destroy_io_queue()
1685 ena_com_destroy_io_sq(ena_dev, io_sq); in ena_com_destroy_io_queue()
1686 ena_com_destroy_io_cq(ena_dev, io_cq); in ena_com_destroy_io_queue()
1688 ena_com_io_queue_free(ena_dev, io_sq, io_cq); in ena_com_destroy_io_queue()
1691 int ena_com_get_link_params(struct ena_com_dev *ena_dev, in ena_com_get_link_params() argument
1694 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG); in ena_com_get_link_params()
1697 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, in ena_com_get_dev_attr_feat() argument
1703 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1710 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; in ena_com_get_dev_attr_feat()
1712 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1719 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size; in ena_com_get_dev_attr_feat()
1721 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1729 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_get_dev_attr_feat()
1740 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS); in ena_com_get_dev_attr_feat()
1754 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) in ena_com_admin_q_comp_intr_handler() argument
1756 ena_com_handle_admin_completion(&ena_dev->admin_queue); in ena_com_admin_q_comp_intr_handler()
1835 int ena_com_dev_reset(struct ena_com_dev *ena_dev, in ena_com_dev_reset() argument
1841 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); in ena_com_dev_reset()
1842 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); in ena_com_dev_reset()
1866 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); in ena_com_dev_reset()
1869 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); in ena_com_dev_reset()
1871 rc = wait_for_reset_state(ena_dev, timeout, in ena_com_dev_reset()
1879 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); in ena_com_dev_reset()
1880 rc = wait_for_reset_state(ena_dev, timeout, 0); in ena_com_dev_reset()
1890 ena_dev->admin_queue.completion_timeout = timeout * 100000; in ena_com_dev_reset()
1892 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; in ena_com_dev_reset()
1897 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, in ena_get_dev_stats() argument
1906 admin_queue = &ena_dev->admin_queue; in ena_get_dev_stats()
1924 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, in ena_com_get_dev_basic_stats() argument
1931 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); in ena_com_get_dev_basic_stats()
1939 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) in ena_com_set_dev_mtu() argument
1946 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { in ena_com_set_dev_mtu()
1952 admin_queue = &ena_dev->admin_queue; in ena_com_set_dev_mtu()
1971 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, in ena_com_get_offload_settings() argument
1977 ret = ena_com_get_feature(ena_dev, &resp, in ena_com_get_offload_settings()
1989 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) in ena_com_set_hash_function() argument
1991 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_set_hash_function()
1992 struct ena_rss *rss = &ena_dev->rss; in ena_com_set_hash_function()
1998 if (!ena_com_check_supported_feature_id(ena_dev, in ena_com_set_hash_function()
2006 ret = ena_com_get_feature(ena_dev, &get_resp, in ena_com_set_hash_function()
2026 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_hash_function()
2050 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, in ena_com_fill_hash_function() argument
2054 struct ena_rss *rss = &ena_dev->rss; in ena_com_fill_hash_function()
2064 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_fill_hash_function()
2096 rc = ena_com_set_hash_function(ena_dev); in ena_com_fill_hash_function()
2100 ena_com_get_hash_function(ena_dev, NULL, NULL); in ena_com_fill_hash_function()
2105 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, in ena_com_get_hash_function() argument
2109 struct ena_rss *rss = &ena_dev->rss; in ena_com_get_hash_function()
2115 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_get_hash_function()
2132 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, in ena_com_get_hash_ctrl() argument
2136 struct ena_rss *rss = &ena_dev->rss; in ena_com_get_hash_ctrl()
2140 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_get_hash_ctrl()
2153 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) in ena_com_set_hash_ctrl() argument
2155 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_set_hash_ctrl()
2156 struct ena_rss *rss = &ena_dev->rss; in ena_com_set_hash_ctrl()
2162 if (!ena_com_check_supported_feature_id(ena_dev, in ena_com_set_hash_ctrl()
2179 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_hash_ctrl()
2199 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) in ena_com_set_default_hash_ctrl() argument
2201 struct ena_rss *rss = &ena_dev->rss; in ena_com_set_default_hash_ctrl()
2208 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); in ena_com_set_default_hash_ctrl()
2251 rc = ena_com_set_hash_ctrl(ena_dev); in ena_com_set_default_hash_ctrl()
2255 ena_com_get_hash_ctrl(ena_dev, 0, NULL); in ena_com_set_default_hash_ctrl()
2260 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, in ena_com_fill_hash_ctrl() argument
2264 struct ena_rss *rss = &ena_dev->rss; in ena_com_fill_hash_ctrl()
2275 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); in ena_com_fill_hash_ctrl()
2288 rc = ena_com_set_hash_ctrl(ena_dev); in ena_com_fill_hash_ctrl()
2292 ena_com_get_hash_ctrl(ena_dev, 0, NULL); in ena_com_fill_hash_ctrl()
2297 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, in ena_com_indirect_table_fill_entry() argument
2300 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_fill_entry()
2313 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) in ena_com_indirect_table_set() argument
2315 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; in ena_com_indirect_table_set()
2316 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_set()
2322 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { in ena_com_indirect_table_set()
2328 ret = ena_com_ind_tbl_convert_to_device(ena_dev); in ena_com_indirect_table_set()
2343 ret = ena_com_mem_addr_set(ena_dev, in ena_com_indirect_table_set()
2366 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) in ena_com_indirect_table_get() argument
2368 struct ena_rss *rss = &ena_dev->rss; in ena_com_indirect_table_get()
2376 rc = ena_com_get_feature_ex(ena_dev, &get_resp, in ena_com_indirect_table_get()
2386 rc = ena_com_ind_tbl_convert_from_device(ena_dev); in ena_com_indirect_table_get()
2396 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) in ena_com_rss_init() argument
2400 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); in ena_com_rss_init()
2402 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); in ena_com_rss_init()
2406 rc = ena_com_hash_key_allocate(ena_dev); in ena_com_rss_init()
2410 rc = ena_com_hash_ctrl_init(ena_dev); in ena_com_rss_init()
2417 ena_com_hash_key_destroy(ena_dev); in ena_com_rss_init()
2419 ena_com_indirect_table_destroy(ena_dev); in ena_com_rss_init()
2425 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) in ena_com_rss_destroy() argument
2427 ena_com_indirect_table_destroy(ena_dev); in ena_com_rss_destroy()
2428 ena_com_hash_key_destroy(ena_dev); in ena_com_rss_destroy()
2429 ena_com_hash_ctrl_destroy(ena_dev); in ena_com_rss_destroy()
2431 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); in ena_com_rss_destroy()
2434 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) in ena_com_allocate_host_info() argument
2436 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_allocate_host_info()
2439 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K, in ena_com_allocate_host_info()
2447 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, in ena_com_allocate_debug_area() argument
2450 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_allocate_debug_area()
2453 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size, in ena_com_allocate_debug_area()
2465 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) in ena_com_delete_host_info() argument
2467 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_delete_host_info()
2470 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, in ena_com_delete_host_info()
2476 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) in ena_com_delete_debug_area() argument
2478 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_delete_debug_area()
2481 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, in ena_com_delete_debug_area()
2488 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) in ena_com_set_host_attributes() argument
2490 struct ena_host_attribute *host_attr = &ena_dev->host_attr; in ena_com_set_host_attributes()
2502 admin_queue = &ena_dev->admin_queue; in ena_com_set_host_attributes()
2507 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_host_attributes()
2515 ret = ena_com_mem_addr_set(ena_dev, in ena_com_set_host_attributes()
2538 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) in ena_com_interrupt_moderation_supported() argument
2540 return ena_com_check_supported_feature_id(ena_dev, in ena_com_interrupt_moderation_supported()
2544 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, in ena_com_update_nonadaptive_moderation_interval_tx() argument
2547 if (!ena_dev->intr_delay_resolution) { in ena_com_update_nonadaptive_moderation_interval_tx()
2552 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs / in ena_com_update_nonadaptive_moderation_interval_tx()
2553 ena_dev->intr_delay_resolution; in ena_com_update_nonadaptive_moderation_interval_tx()
2558 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, in ena_com_update_nonadaptive_moderation_interval_rx() argument
2561 if (!ena_dev->intr_delay_resolution) { in ena_com_update_nonadaptive_moderation_interval_rx()
2569 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = in ena_com_update_nonadaptive_moderation_interval_rx()
2570 rx_coalesce_usecs / ena_dev->intr_delay_resolution; in ena_com_update_nonadaptive_moderation_interval_rx()
2575 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev) in ena_com_destroy_interrupt_moderation() argument
2577 if (ena_dev->intr_moder_tbl) in ena_com_destroy_interrupt_moderation()
2578 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl); in ena_com_destroy_interrupt_moderation()
2579 ena_dev->intr_moder_tbl = NULL; in ena_com_destroy_interrupt_moderation()
2582 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) in ena_com_init_interrupt_moderation() argument
2588 rc = ena_com_get_feature(ena_dev, &get_resp, in ena_com_init_interrupt_moderation()
2602 ena_com_disable_adaptive_moderation(ena_dev); in ena_com_init_interrupt_moderation()
2606 rc = ena_com_init_interrupt_moderation_table(ena_dev); in ena_com_init_interrupt_moderation()
2612 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); in ena_com_init_interrupt_moderation()
2613 ena_com_enable_adaptive_moderation(ena_dev); in ena_com_init_interrupt_moderation()
2617 ena_com_destroy_interrupt_moderation(ena_dev); in ena_com_init_interrupt_moderation()
2621 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev) in ena_com_config_default_interrupt_moderation_table() argument
2623 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; in ena_com_config_default_interrupt_moderation_table()
2664 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) in ena_com_get_nonadaptive_moderation_interval_tx() argument
2666 return ena_dev->intr_moder_tx_interval; in ena_com_get_nonadaptive_moderation_interval_tx()
2669 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) in ena_com_get_nonadaptive_moderation_interval_rx() argument
2671 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; in ena_com_get_nonadaptive_moderation_interval_rx()
2679 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, in ena_com_init_intr_moderation_entry() argument
2683 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; in ena_com_init_intr_moderation_entry()
2689 if (ena_dev->intr_delay_resolution) in ena_com_init_intr_moderation_entry()
2691 ena_dev->intr_delay_resolution; in ena_com_init_intr_moderation_entry()
2699 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, in ena_com_get_intr_moderation_entry() argument
2703 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; in ena_com_get_intr_moderation_entry()
2709 if (ena_dev->intr_delay_resolution) in ena_com_get_intr_moderation_entry()
2710 entry->intr_moder_interval *= ena_dev->intr_delay_resolution; in ena_com_get_intr_moderation_entry()