155 	u32 addr_low, addr_high, aenq_caps;  in ena_com_admin_init_aenq()  local
171 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);  in ena_com_admin_init_aenq()
174 	writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);  in ena_com_admin_init_aenq()
1516 	u32 addr_low, addr_high;  in ena_com_mmio_reg_read_request_write_dev_addr()  local
1518 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);  in ena_com_mmio_reg_read_request_write_dev_addr()
1521 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
1530 	u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;  in ena_com_admin_init()  local
1571 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);  in ena_com_admin_init()
1574 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);  in ena_com_admin_init()
1577 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);  in ena_com_admin_init()
1580 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);  in ena_com_admin_init()