Lines Matching refs:nandc
192 #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \ argument
193 nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
202 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
479 static void free_bam_transaction(struct qcom_nand_controller *nandc) in free_bam_transaction() argument
481 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
483 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
488 alloc_bam_transaction(struct qcom_nand_controller *nandc) in alloc_bam_transaction() argument
492 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
501 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
524 static void clear_bam_transaction(struct qcom_nand_controller *nandc) in clear_bam_transaction() argument
526 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
528 if (!nandc->props->is_bam) in clear_bam_transaction()
542 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
544 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
580 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
582 return ioread32(nandc->base + offset); in nandc_read()
585 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
588 iowrite32(val, nandc->base + offset); in nandc_write()
591 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, in nandc_read_buffer_sync() argument
594 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
598 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
600 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
603 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
605 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
655 static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, in nandc_set_reg() argument
658 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
671 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in set_address() local
676 nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); in set_address()
677 nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); in set_address()
690 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in update_rw_regs() local
716 nandc_set_reg(nandc, NAND_FLASH_CMD, cmd); in update_rw_regs()
717 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
718 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); in update_rw_regs()
719 nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg); in update_rw_regs()
720 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); in update_rw_regs()
721 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in update_rw_regs()
722 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in update_rw_regs()
723 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in update_rw_regs()
726 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ? in update_rw_regs()
735 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, in prepare_bam_async_desc() argument
743 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
751 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
757 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
772 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
774 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
786 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
787 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
795 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
800 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
814 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_cmd() argument
821 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
829 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
831 reg_buf_dma_addr(nandc, in prep_bam_dma_desc_cmd()
835 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
854 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
869 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_data() argument
874 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
890 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
900 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, in prep_adm_dma_desc() argument
927 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
938 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
939 slave_conf.slave_id = nandc->data_crci; in prep_adm_dma_desc()
942 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
943 slave_conf.slave_id = nandc->cmd_crci; in prep_adm_dma_desc()
946 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
948 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
952 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
954 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
961 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
978 static int read_reg_dma(struct qcom_nand_controller *nandc, int first, in read_reg_dma() argument
984 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
985 nandc->reg_read_pos += num_regs; in read_reg_dma()
988 first = dev_cmd_reg_addr(nandc, first); in read_reg_dma()
990 if (nandc->props->is_bam) in read_reg_dma()
991 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, in read_reg_dma()
997 return prep_adm_dma_desc(nandc, true, first, vaddr, in read_reg_dma()
1009 static int write_reg_dma(struct qcom_nand_controller *nandc, int first, in write_reg_dma() argument
1013 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1029 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); in write_reg_dma()
1032 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); in write_reg_dma()
1034 if (nandc->props->is_bam) in write_reg_dma()
1035 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, in write_reg_dma()
1041 return prep_adm_dma_desc(nandc, false, first, vaddr, in write_reg_dma()
1054 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1057 if (nandc->props->is_bam) in read_data_dma()
1058 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); in read_data_dma()
1060 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1072 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1075 if (nandc->props->is_bam) in write_data_dma()
1076 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); in write_data_dma()
1078 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1085 static void config_nand_page_read(struct qcom_nand_controller *nandc) in config_nand_page_read() argument
1087 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_read()
1088 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
1089 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
1090 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); in config_nand_page_read()
1091 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, in config_nand_page_read()
1100 config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc) in config_nand_cw_read() argument
1102 if (nandc->props->is_bam) in config_nand_cw_read()
1103 write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, in config_nand_cw_read()
1106 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1107 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1110 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); in config_nand_cw_read()
1111 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, in config_nand_cw_read()
1114 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1123 config_nand_single_cw_page_read(struct qcom_nand_controller *nandc, in config_nand_single_cw_page_read() argument
1126 config_nand_page_read(nandc); in config_nand_single_cw_page_read()
1127 config_nand_cw_read(nandc, use_ecc); in config_nand_single_cw_page_read()
1134 static void config_nand_page_write(struct qcom_nand_controller *nandc) in config_nand_page_write() argument
1136 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_write()
1137 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
1138 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
1146 static void config_nand_cw_write(struct qcom_nand_controller *nandc) in config_nand_cw_write() argument
1148 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1149 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1151 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1153 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
1154 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1166 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_param() local
1173 nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE); in nandc_param()
1174 nandc_set_reg(nandc, NAND_ADDR0, 0); in nandc_param()
1175 nandc_set_reg(nandc, NAND_ADDR1, 0); in nandc_param()
1176 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE in nandc_param()
1180 nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES in nandc_param()
1187 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); in nandc_param()
1190 nandc_set_reg(nandc, NAND_DEV_CMD_VLD, in nandc_param()
1191 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1192 nandc_set_reg(nandc, NAND_DEV_CMD1, in nandc_param()
1193 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1196 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in nandc_param()
1198 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1199 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1200 nandc_set_read_loc(nandc, 0, 0, 512, 1); in nandc_param()
1202 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); in nandc_param()
1203 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1205 nandc->buf_count = 512; in nandc_param()
1206 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1208 config_nand_single_cw_page_read(nandc, false); in nandc_param()
1210 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1211 nandc->buf_count, 0); in nandc_param()
1214 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); in nandc_param()
1215 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1224 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in erase_block() local
1226 nandc_set_reg(nandc, NAND_FLASH_CMD, in erase_block()
1228 nandc_set_reg(nandc, NAND_ADDR0, page_addr); in erase_block()
1229 nandc_set_reg(nandc, NAND_ADDR1, 0); in erase_block()
1230 nandc_set_reg(nandc, NAND_DEV0_CFG0, in erase_block()
1232 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw); in erase_block()
1233 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in erase_block()
1234 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in erase_block()
1235 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in erase_block()
1237 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in erase_block()
1238 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in erase_block()
1239 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in erase_block()
1241 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1243 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in erase_block()
1244 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1253 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_id() local
1258 nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID); in read_id()
1259 nandc_set_reg(nandc, NAND_ADDR0, column); in read_id()
1260 nandc_set_reg(nandc, NAND_ADDR1, 0); in read_id()
1261 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, in read_id()
1262 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1263 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in read_id()
1265 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in read_id()
1266 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in read_id()
1268 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); in read_id()
1277 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in reset() local
1279 nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE); in reset()
1280 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in reset()
1282 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1283 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1285 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in reset()
1291 static int submit_descs(struct qcom_nand_controller *nandc) in submit_descs() argument
1295 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1298 if (nandc->props->is_bam) { in submit_descs()
1300 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1306 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1313 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1320 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1323 if (nandc->props->is_bam) { in submit_descs()
1332 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1333 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1334 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1340 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1347 static void free_descs(struct qcom_nand_controller *nandc) in free_descs() argument
1351 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1354 if (nandc->props->is_bam) in free_descs()
1355 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1358 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1366 static void clear_read_regs(struct qcom_nand_controller *nandc) in clear_read_regs() argument
1368 nandc->reg_read_pos = 0; in clear_read_regs()
1369 nandc_read_buffer_sync(nandc, false); in clear_read_regs()
1375 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in pre_command() local
1377 nandc->buf_count = 0; in pre_command()
1378 nandc->buf_start = 0; in pre_command()
1382 clear_read_regs(nandc); in pre_command()
1386 clear_bam_transaction(nandc); in pre_command()
1397 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_erase_write_errors() local
1403 nandc_read_buffer_sync(nandc, true); in parse_erase_write_errors()
1406 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1421 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in post_command() local
1425 nandc_read_buffer_sync(nandc, true); in post_command()
1426 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1427 nandc->buf_count); in post_command()
1450 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_command() local
1463 nandc->buf_count = 4; in qcom_nandc_command()
1500 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1502 free_descs(nandc); in qcom_nandc_command()
1507 ret = submit_descs(nandc); in qcom_nandc_command()
1509 dev_err(nandc->dev, in qcom_nandc_command()
1514 free_descs(nandc); in qcom_nandc_command()
1577 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in check_flash_errors() local
1581 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1596 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_cw_raw() local
1604 clear_bam_transaction(nandc); in qcom_nandc_read_cw_raw()
1607 config_nand_page_read(nandc); in qcom_nandc_read_cw_raw()
1622 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1623 nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); in qcom_nandc_read_cw_raw()
1626 nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); in qcom_nandc_read_cw_raw()
1629 nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); in qcom_nandc_read_cw_raw()
1632 nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); in qcom_nandc_read_cw_raw()
1635 config_nand_cw_read(nandc, false); in qcom_nandc_read_cw_raw()
1637 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_cw_raw()
1640 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); in qcom_nandc_read_cw_raw()
1643 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); in qcom_nandc_read_cw_raw()
1646 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); in qcom_nandc_read_cw_raw()
1648 ret = submit_descs(nandc); in qcom_nandc_read_cw_raw()
1649 free_descs(nandc); in qcom_nandc_read_cw_raw()
1651 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1739 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_read_errors() local
1748 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1749 nandc_read_buffer_sync(nandc, true); in parse_read_errors()
1843 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_page_ecc() local
1848 config_nand_page_read(nandc); in read_page_ecc()
1863 if (nandc->props->is_bam) { in read_page_ecc()
1865 nandc_set_read_loc(nandc, 0, 0, data_size, 0); in read_page_ecc()
1866 nandc_set_read_loc(nandc, 1, data_size, in read_page_ecc()
1869 nandc_set_read_loc(nandc, 0, 0, data_size, 1); in read_page_ecc()
1871 nandc_set_read_loc(nandc, 0, data_size, in read_page_ecc()
1876 config_nand_cw_read(nandc, true); in read_page_ecc()
1879 read_data_dma(nandc, FLASH_BUF_ACC, data_buf, in read_page_ecc()
1895 read_data_dma(nandc, FLASH_BUF_ACC + data_size, in read_page_ecc()
1905 ret = submit_descs(nandc); in read_page_ecc()
1906 free_descs(nandc); in read_page_ecc()
1909 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
1923 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in copy_last_cw() local
1928 clear_read_regs(nandc); in copy_last_cw()
1933 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
1938 config_nand_single_cw_page_read(nandc, host->use_ecc); in copy_last_cw()
1940 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
1942 ret = submit_descs(nandc); in copy_last_cw()
1944 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
1946 free_descs(nandc); in copy_last_cw()
1956 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_page() local
1963 clear_bam_transaction(nandc); in qcom_nandc_read_page()
1996 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_oob() local
1999 clear_read_regs(nandc); in qcom_nandc_read_oob()
2000 clear_bam_transaction(nandc); in qcom_nandc_read_oob()
2014 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page() local
2021 clear_read_regs(nandc); in qcom_nandc_write_page()
2022 clear_bam_transaction(nandc); in qcom_nandc_write_page()
2029 config_nand_page_write(nandc); in qcom_nandc_write_page()
2044 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, in qcom_nandc_write_page()
2057 write_data_dma(nandc, FLASH_BUF_ACC + data_size, in qcom_nandc_write_page()
2061 config_nand_cw_write(nandc); in qcom_nandc_write_page()
2067 ret = submit_descs(nandc); in qcom_nandc_write_page()
2069 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2071 free_descs(nandc); in qcom_nandc_write_page()
2085 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page_raw() local
2091 clear_read_regs(nandc); in qcom_nandc_write_page_raw()
2092 clear_bam_transaction(nandc); in qcom_nandc_write_page_raw()
2099 config_nand_page_write(nandc); in qcom_nandc_write_page_raw()
2118 write_data_dma(nandc, reg_off, data_buf, data_size1, in qcom_nandc_write_page_raw()
2123 write_data_dma(nandc, reg_off, oob_buf, oob_size1, in qcom_nandc_write_page_raw()
2128 write_data_dma(nandc, reg_off, data_buf, data_size2, in qcom_nandc_write_page_raw()
2133 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); in qcom_nandc_write_page_raw()
2136 config_nand_cw_write(nandc); in qcom_nandc_write_page_raw()
2139 ret = submit_descs(nandc); in qcom_nandc_write_page_raw()
2141 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2143 free_descs(nandc); in qcom_nandc_write_page_raw()
2162 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_oob() local
2169 clear_bam_transaction(nandc); in qcom_nandc_write_oob()
2175 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2177 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2183 config_nand_page_write(nandc); in qcom_nandc_write_oob()
2184 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_write_oob()
2185 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2186 config_nand_cw_write(nandc); in qcom_nandc_write_oob()
2188 ret = submit_descs(nandc); in qcom_nandc_write_oob()
2190 free_descs(nandc); in qcom_nandc_write_oob()
2193 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2204 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_bad() local
2218 clear_bam_transaction(nandc); in qcom_nandc_block_bad()
2224 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2230 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2233 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2242 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_markbad() local
2246 clear_read_regs(nandc); in qcom_nandc_block_markbad()
2247 clear_bam_transaction(nandc); in qcom_nandc_block_markbad()
2254 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2263 config_nand_page_write(nandc); in qcom_nandc_block_markbad()
2264 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_block_markbad()
2265 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2266 config_nand_cw_write(nandc); in qcom_nandc_block_markbad()
2268 ret = submit_descs(nandc); in qcom_nandc_block_markbad()
2270 free_descs(nandc); in qcom_nandc_block_markbad()
2273 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2290 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_byte() local
2291 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2302 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2303 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2311 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_buf() local
2312 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2314 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2315 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2322 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_buf() local
2323 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2325 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2327 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2334 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_select_chip() local
2339 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2483 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nand_attach_chip() local
2500 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2524 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2571 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2629 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2631 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2634 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2647 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) in qcom_nandc_alloc() argument
2651 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2653 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2663 nandc->buf_size = 532; in qcom_nandc_alloc()
2665 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2667 if (!nandc->data_buffer) in qcom_nandc_alloc()
2670 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2672 if (!nandc->regs) in qcom_nandc_alloc()
2675 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2676 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2678 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2681 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2682 nandc->reg_read_dma = in qcom_nandc_alloc()
2683 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2685 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2687 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2688 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2692 nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx"); in qcom_nandc_alloc()
2693 if (!nandc->tx_chan) { in qcom_nandc_alloc()
2694 dev_err(nandc->dev, "failed to request tx channel\n"); in qcom_nandc_alloc()
2698 nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx"); in qcom_nandc_alloc()
2699 if (!nandc->rx_chan) { in qcom_nandc_alloc()
2700 dev_err(nandc->dev, "failed to request rx channel\n"); in qcom_nandc_alloc()
2704 nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd"); in qcom_nandc_alloc()
2705 if (!nandc->cmd_chan) { in qcom_nandc_alloc()
2706 dev_err(nandc->dev, "failed to request cmd channel\n"); in qcom_nandc_alloc()
2716 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2717 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2718 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2719 dev_err(nandc->dev, in qcom_nandc_alloc()
2724 nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2725 if (!nandc->chan) { in qcom_nandc_alloc()
2726 dev_err(nandc->dev, in qcom_nandc_alloc()
2732 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2733 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2735 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2736 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
2741 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) in qcom_nandc_unalloc() argument
2743 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2744 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2745 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2747 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2750 if (nandc->tx_chan) in qcom_nandc_unalloc()
2751 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2753 if (nandc->rx_chan) in qcom_nandc_unalloc()
2754 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2756 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2757 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2759 if (nandc->chan) in qcom_nandc_unalloc()
2760 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2765 static int qcom_nandc_setup(struct qcom_nand_controller *nandc) in qcom_nandc_setup() argument
2770 nandc_write(nandc, SFLASHC_BURST_CFG, 0); in qcom_nandc_setup()
2771 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), in qcom_nandc_setup()
2775 if (nandc->props->is_bam) { in qcom_nandc_setup()
2776 nand_ctrl = nandc_read(nandc, NAND_CTRL); in qcom_nandc_setup()
2777 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); in qcom_nandc_setup()
2779 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); in qcom_nandc_setup()
2783 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2784 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2789 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, in qcom_nand_host_init_and_register() argument
2795 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2831 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
2849 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) in qcom_probe_nand_devices() argument
2851 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2856 if (nandc->props->is_bam) { in qcom_probe_nand_devices()
2857 free_bam_transaction(nandc); in qcom_probe_nand_devices()
2858 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_probe_nand_devices()
2859 if (!nandc->bam_txn) { in qcom_probe_nand_devices()
2860 dev_err(nandc->dev, in qcom_probe_nand_devices()
2873 ret = qcom_nand_host_init_and_register(nandc, host, child); in qcom_probe_nand_devices()
2879 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2882 if (list_empty(&nandc->host_list)) in qcom_probe_nand_devices()
2891 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_parse_dt() local
2892 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
2895 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
2897 &nandc->cmd_crci); in qcom_nandc_parse_dt()
2899 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
2904 &nandc->data_crci); in qcom_nandc_parse_dt()
2906 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
2916 struct qcom_nand_controller *nandc; in qcom_nandc_probe() local
2922 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
2923 if (!nandc) in qcom_nandc_probe()
2926 platform_set_drvdata(pdev, nandc); in qcom_nandc_probe()
2927 nandc->dev = dev; in qcom_nandc_probe()
2935 nandc->props = dev_data; in qcom_nandc_probe()
2937 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
2938 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
2939 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
2941 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
2942 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
2943 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
2950 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
2951 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
2952 return PTR_ERR(nandc->base); in qcom_nandc_probe()
2954 nandc->base_phys = res->start; in qcom_nandc_probe()
2955 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
2958 if (!nandc->base_dma) in qcom_nandc_probe()
2961 ret = qcom_nandc_alloc(nandc); in qcom_nandc_probe()
2965 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
2969 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
2973 ret = qcom_nandc_setup(nandc); in qcom_nandc_probe()
2977 ret = qcom_probe_nand_devices(nandc); in qcom_nandc_probe()
2984 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
2986 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
2988 qcom_nandc_unalloc(nandc); in qcom_nandc_probe()
2998 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_remove() local
3002 list_for_each_entry(host, &nandc->host_list, node) in qcom_nandc_remove()
3006 qcom_nandc_unalloc(nandc); in qcom_nandc_remove()
3008 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3009 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3011 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()