181 		out_be32(&lbc->fbar, page_addr >> 6);  in set_addr()
182 		out_be32(&lbc->fpar,  in set_addr()
191 		out_be32(&lbc->fbar, page_addr >> 5);  in set_addr()
192 		out_be32(&lbc->fpar,  in set_addr()
225 	out_be32(&lbc->fmr, priv->fmr | 3);  in fsl_elbc_run_command()
227 		out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);  in fsl_elbc_run_command()
240 	out_be32(&lbc->lsor, priv->bank);  in fsl_elbc_run_command()
279 			out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */  in fsl_elbc_run_command()
296 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
303 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |  in fsl_elbc_do_read()
306 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
313 			out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
315 			out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
348 		out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */  in fsl_elbc_cmdfunc()
364 		out_be32(&lbc->fbcr, mtd->oobsize - column);  in fsl_elbc_cmdfunc()
377 		out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |  in fsl_elbc_cmdfunc()
380 		out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
385 		out_be32(&lbc->fbcr, 256);  in fsl_elbc_cmdfunc()
405 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
412 		out_be32(&lbc->fcr,  in fsl_elbc_cmdfunc()
417 		out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
449 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
458 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
476 		out_be32(&lbc->fcr, fcr);  in fsl_elbc_cmdfunc()
493 			out_be32(&lbc->fbcr,  in fsl_elbc_cmdfunc()
496 			out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
505 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
508 		out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
509 		out_be32(&lbc->fbcr, 1);  in fsl_elbc_cmdfunc()
524 		out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);  in fsl_elbc_cmdfunc()
525 		out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()