217 	u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);  in wmt_set_sd_power()
240 				tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP);  in wmt_mci_read_response()
242 				tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP +  in wmt_mci_read_response()
254 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);  in wmt_mci_start_command()
272 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);  in wmt_mci_send_command()
285 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);  in wmt_mci_send_command()
385 	status0 = readb(priv->sdmmc_base + SDMMC_STS0);  in wmt_mci_regular_isr()
386 	status1 = readb(priv->sdmmc_base + SDMMC_STS1);  in wmt_mci_regular_isr()
387 	status2 = readb(priv->sdmmc_base + SDMMC_STS2);  in wmt_mci_regular_isr()
390 	reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);  in wmt_mci_regular_isr()
474 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);  in wmt_reset_hardware()
478 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);  in wmt_reset_hardware()
498 	reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);  in wmt_reset_hardware()
692 	busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);  in wmt_mci_set_ios()
693 	extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);  in wmt_mci_set_ios()
718 	return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT);  in wmt_mci_get_ro()
724 	u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3;  in wmt_mci_get_cd()
896 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);  in wmt_mci_remove()
938 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);  in wmt_mci_suspend()
962 		reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);  in wmt_mci_resume()
970 		reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);  in wmt_mci_resume()