719 				   struct mmc_ios *ios, u32 rate)  in sunxi_mmc_clk_set_phase()  argument
737 		if (ios->timing != MMC_TIMING_UHS_DDR50 &&  in sunxi_mmc_clk_set_phase()
738 		    ios->timing != MMC_TIMING_MMC_DDR52) {  in sunxi_mmc_clk_set_phase()
740 		} else if (ios->bus_width == MMC_BUS_WIDTH_8) {  in sunxi_mmc_clk_set_phase()
757 				  struct mmc_ios *ios)  in sunxi_mmc_clk_set_rate()  argument
761 	u32 rval, clock = ios->clock, div = 1;  in sunxi_mmc_clk_set_rate()
771 	if (!ios->clock)  in sunxi_mmc_clk_set_rate()
783 	if (ios->timing == MMC_TIMING_MMC_DDR52 &&  in sunxi_mmc_clk_set_rate()
785 	     ios->bus_width == MMC_BUS_WIDTH_8)) {  in sunxi_mmc_clk_set_rate()
833 	ret = sunxi_mmc_clk_set_phase(host, ios, rate);  in sunxi_mmc_clk_set_rate()
875 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)  in sunxi_mmc_set_clk()  argument
881 	if (ios->timing == MMC_TIMING_UHS_DDR50 ||  in sunxi_mmc_set_clk()
882 	    ios->timing == MMC_TIMING_MMC_DDR52)  in sunxi_mmc_set_clk()
888 	host->ferror = sunxi_mmc_clk_set_rate(host, ios);  in sunxi_mmc_set_clk()
893 				 struct mmc_ios *ios)  in sunxi_mmc_card_power()  argument
897 	switch (ios->power_mode) {  in sunxi_mmc_card_power()
904 							     ios->vdd);  in sunxi_mmc_card_power()
938 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)  in sunxi_mmc_set_ios()  argument
942 	sunxi_mmc_card_power(host, ios);  in sunxi_mmc_set_ios()
943 	sunxi_mmc_set_bus_width(host, ios->bus_width);  in sunxi_mmc_set_ios()
944 	sunxi_mmc_set_clk(host, ios);  in sunxi_mmc_set_ios()
947 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)  in sunxi_mmc_volt_switch()  argument
951 		return mmc_regulator_set_vqmmc(mmc, ios);  in sunxi_mmc_volt_switch()
954 	if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)  in sunxi_mmc_volt_switch()
1450 	sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);  in sunxi_mmc_runtime_resume()
1451 	sunxi_mmc_set_clk(host, &mmc->ios);  in sunxi_mmc_runtime_resume()