Lines Matching refs:scratch_32
140 u32 scratch_32; in o2_pci_set_baseclk() local
142 O2_SD_PLL_SETTING, &scratch_32); in o2_pci_set_baseclk()
144 scratch_32 &= 0x0000FFFF; in o2_pci_set_baseclk()
145 scratch_32 |= value; in o2_pci_set_baseclk()
148 O2_SD_PLL_SETTING, scratch_32); in o2_pci_set_baseclk()
154 u32 scratch_32; in o2_pci_led_enable() local
158 O2_SD_FUNC_REG0, &scratch_32); in o2_pci_led_enable()
162 scratch_32 &= ~O2_SD_FREG0_LEDOFF; in o2_pci_led_enable()
164 O2_SD_FUNC_REG0, scratch_32); in o2_pci_led_enable()
167 O2_SD_TEST_REG, &scratch_32); in o2_pci_led_enable()
171 scratch_32 |= O2_SD_LED_ENABLE; in o2_pci_led_enable()
173 O2_SD_TEST_REG, scratch_32); in o2_pci_led_enable()
179 u32 scratch_32; in sdhci_pci_o2_fujin2_pci_init() local
182 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
185 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14)); in sdhci_pci_o2_fujin2_pci_init()
186 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
189 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
192 scratch_32 &= ~((1 << 19) | (1 << 11)); in sdhci_pci_o2_fujin2_pci_init()
193 scratch_32 |= (1 << 10); in sdhci_pci_o2_fujin2_pci_init()
194 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
197 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
200 scratch_32 |= (1 << 4); in sdhci_pci_o2_fujin2_pci_init()
201 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
207 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
210 scratch_32 &= ~(3 << 12); in sdhci_pci_o2_fujin2_pci_init()
211 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
214 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
217 scratch_32 &= ~(0x01FE); in sdhci_pci_o2_fujin2_pci_init()
218 scratch_32 |= 0x00CC; in sdhci_pci_o2_fujin2_pci_init()
219 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
222 O2_SD_TUNING_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
225 scratch_32 &= ~(0x000000FF); in sdhci_pci_o2_fujin2_pci_init()
226 scratch_32 |= 0x00000066; in sdhci_pci_o2_fujin2_pci_init()
227 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
231 O2_SD_UHS2_L1_CTRL, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
234 scratch_32 &= ~(0x000000FC); in sdhci_pci_o2_fujin2_pci_init()
235 scratch_32 |= 0x00000084; in sdhci_pci_o2_fujin2_pci_init()
236 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
239 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
242 scratch_32 &= ~((1 << 21) | (1 << 30)); in sdhci_pci_o2_fujin2_pci_init()
244 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
247 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
250 scratch_32 &= ~(0xf0000000); in sdhci_pci_o2_fujin2_pci_init()
251 scratch_32 |= 0x30000000; in sdhci_pci_o2_fujin2_pci_init()
252 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
255 O2_SD_MISC_CTRL4, &scratch_32); in sdhci_pci_o2_fujin2_pci_init()
258 scratch_32 &= ~(0x000f0000); in sdhci_pci_o2_fujin2_pci_init()
259 scratch_32 |= 0x00080000; in sdhci_pci_o2_fujin2_pci_init()
260 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32); in sdhci_pci_o2_fujin2_pci_init()
343 u32 scratch_32; in sdhci_pci_o2_probe() local
415 &scratch_32); in sdhci_pci_o2_probe()
416 scratch_32 = ((scratch_32 & 0xFF000000) >> 24); in sdhci_pci_o2_probe()
419 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) { in sdhci_pci_o2_probe()
420 scratch_32 = 0x25100000; in sdhci_pci_o2_probe()
422 o2_pci_set_baseclk(chip, scratch_32); in sdhci_pci_o2_probe()
425 &scratch_32); in sdhci_pci_o2_probe()
428 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET; in sdhci_pci_o2_probe()
431 scratch_32); in sdhci_pci_o2_probe()
446 O2_SD_CLK_SETTING, &scratch_32); in sdhci_pci_o2_probe()
450 scratch_32 &= ~(0xFF00); in sdhci_pci_o2_probe()
451 scratch_32 |= 0x07E0C800; in sdhci_pci_o2_probe()
453 O2_SD_CLK_SETTING, scratch_32); in sdhci_pci_o2_probe()
456 O2_SD_CLKREQ, &scratch_32); in sdhci_pci_o2_probe()
459 scratch_32 |= 0x3; in sdhci_pci_o2_probe()
460 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32); in sdhci_pci_o2_probe()
463 O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_probe()
467 scratch_32 &= ~(0x1F3F070E); in sdhci_pci_o2_probe()
468 scratch_32 |= 0x18270106; in sdhci_pci_o2_probe()
470 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
474 O2_SD_CAP_REG2, &scratch_32); in sdhci_pci_o2_probe()
477 scratch_32 &= ~(0xE0); in sdhci_pci_o2_probe()
479 O2_SD_CAP_REG2, scratch_32); in sdhci_pci_o2_probe()
504 O2_SD_PLL_SETTING, &scratch_32); in sdhci_pci_o2_probe()
506 if ((scratch_32 & 0xff000000) == 0x01000000) { in sdhci_pci_o2_probe()
507 scratch_32 &= 0x0000FFFF; in sdhci_pci_o2_probe()
508 scratch_32 |= 0x1F340000; in sdhci_pci_o2_probe()
511 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
513 scratch_32 &= 0x0000FFFF; in sdhci_pci_o2_probe()
514 scratch_32 |= 0x25100000; in sdhci_pci_o2_probe()
517 O2_SD_PLL_SETTING, scratch_32); in sdhci_pci_o2_probe()
521 &scratch_32); in sdhci_pci_o2_probe()
522 scratch_32 |= (1 << 22); in sdhci_pci_o2_probe()
524 O2_SD_FUNC_REG4, scratch_32); in sdhci_pci_o2_probe()