158 	seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));  in dw_mci_regs_show()
159 	seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));  in dw_mci_regs_show()
160 	seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));  in dw_mci_regs_show()
161 	seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));  in dw_mci_regs_show()
162 	seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));  in dw_mci_regs_show()
163 	seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));  in dw_mci_regs_show()
217 	ctrl = mci_readl(host, CTRL);  in dw_mci_ctrl_reset()
313 		clk_en_a = mci_readl(host, CLKENA);  in dw_mci_prepare_command()
388 	cto_clks = mci_readl(host, TMOUT) & 0xff;  in dw_mci_set_cto()
389 	cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;  in dw_mci_set_cto()
472 	u32 bmod = mci_readl(host, BMOD);  in dw_mci_idmac_reset()
483 	temp = mci_readl(host, CTRL);  in dw_mci_idmac_stop_dma()
489 	temp = mci_readl(host, BMOD);  in dw_mci_idmac_stop_dma()
766 	temp = mci_readl(host, CTRL);  in dw_mci_idmac_start_dma()
774 	temp = mci_readl(host, BMOD);  in dw_mci_idmac_start_dma()
817 	fifoth_val = mci_readl(host, FIFOTH);  in dw_mci_edmac_start_dma()
994 		present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))  in dw_mci_get_cd()
1136 	temp = mci_readl(host, CTRL);  in dw_mci_submit_data_dma()
1142 	temp = mci_readl(host, INTMASK);  in dw_mci_submit_data_dma()
1192 		temp = mci_readl(host, INTMASK);  in dw_mci_submit_data()
1197 		temp = mci_readl(host, CTRL);  in dw_mci_submit_data()
1448 	regs = mci_readl(slot->host, UHS_REG);  in dw_mci_set_ios()
1483 		regs = mci_readl(slot->host, PWREN);  in dw_mci_set_ios()
1522 		regs = mci_readl(slot->host, PWREN);  in dw_mci_set_ios()
1543 	status = mci_readl(slot->host, STATUS);  in dw_mci_card_busy()
1565 	uhs = mci_readl(host, UHS_REG);  in dw_mci_switch_voltage()
1597 			mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;  in dw_mci_get_ro()
1624 	reset = mci_readl(host, RST_N);  in dw_mci_hw_reset()
1648 		clk_en_a_old = mci_readl(host, CLKENA);  in dw_mci_init_card()
1676 	int_mask = mci_readl(host, INTMASK);  in __dw_mci_enable_sdio_irq()
1778 		if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {  in dw_mci_reset()
1858 			cmd->resp[3] = mci_readl(host, RESP0);  in dw_mci_command_complete()
1859 			cmd->resp[2] = mci_readl(host, RESP1);  in dw_mci_command_complete()
1860 			cmd->resp[1] = mci_readl(host, RESP2);  in dw_mci_command_complete()
1861 			cmd->resp[0] = mci_readl(host, RESP3);  in dw_mci_command_complete()
1863 			cmd->resp[0] = mci_readl(host, RESP0);  in dw_mci_command_complete()
1932 	drto_clks = mci_readl(host, TMOUT) >> 8;  in dw_mci_set_drto()
1933 	drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;  in dw_mci_set_drto()
2531 			fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))  in dw_mci_read_data_pio()
2543 		status = mci_readl(host, MINTSTS);  in dw_mci_read_data_pio()
2547 		 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));  in dw_mci_read_data_pio()
2587 				 SDMMC_GET_FCNT(mci_readl(host, STATUS)))  in dw_mci_write_data_pio()
2599 		status = mci_readl(host, MINTSTS);  in dw_mci_write_data_pio()
2648 	pending = mci_readl(host, MINTSTS); /* read-only mask reg */  in dw_mci_interrupt()
2748 		pending = mci_readl(host, IDSTS64);  in dw_mci_interrupt()
2757 		pending = mci_readl(host, IDSTS);  in dw_mci_interrupt()
2920 	host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));  in dw_mci_init_dma()
2936 		addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));  in dw_mci_init_dma()
3026 	pending = mci_readl(host, MINTSTS); /* read-only mask reg */  in dw_mci_cto_timer()
3077 	pending = mci_readl(host, MINTSTS); /* read-only mask reg */  in dw_mci_dto_timer()
3181 		temp = mci_readl(host, INTMASK);  in dw_mci_enable_cd()
3270 	i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));  in dw_mci_probe()
3319 		fifo_size = mci_readl(host, FIFOTH);  in dw_mci_probe()
3337 	host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));  in dw_mci_probe()