Lines Matching refs:bus_width
827 int clk_period = 0, power_class = 10, bus_width = 0; in cvm_mmc_set_ios() local
855 switch (ios->bus_width) { in cvm_mmc_set_ios()
857 bus_width = 2; in cvm_mmc_set_ios()
860 bus_width = 1; in cvm_mmc_set_ios()
863 bus_width = 0; in cvm_mmc_set_ios()
868 if (ios->bus_width && ios->timing == MMC_TIMING_MMC_DDR52) in cvm_mmc_set_ios()
869 bus_width |= 4; in cvm_mmc_set_ios()
882 FIELD_PREP(MIO_EMM_SWITCH_BUS_WIDTH, bus_width) | in cvm_mmc_set_ios()
952 u32 id, cmd_skew = 0, dat_skew = 0, bus_width = 0; in cvm_mmc_of_parse() local
986 of_property_read_u32(node, "cavium,bus-max-width", &bus_width); in cvm_mmc_of_parse()
987 if (bus_width == 8) in cvm_mmc_of_parse()
989 else if (bus_width == 4) in cvm_mmc_of_parse()