Lines Matching refs:cxl_p1n_reg_t

56 } cxl_p1n_reg_t;  typedef
123 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
124 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
125 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
126 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
127 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
128 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
130 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
132 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
134 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
135 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
136 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
138 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
139 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
140 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
141 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
143 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
144 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
146 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
147 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
148 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
149 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
798 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)  in _cxl_p1n_addr()
804 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)  in cxl_p1n_write()
810 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)  in cxl_p1n_read()