Lines Matching refs:cxl_p1_reg_t

53 } cxl_p1_reg_t;  typedef
67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
69 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
70 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
73 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
74 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
77 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
78 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
79 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
80 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
81 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
82 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
86 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
87 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
88 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
89 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
95 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
97 static const cxl_p1_reg_t CXL_PSL9_CONTROL  = {0x0020};
98 static const cxl_p1_reg_t CXL_XSL9_INV      = {0x0110};
99 static const cxl_p1_reg_t CXL_XSL9_DBG      = {0x0130};
100 static const cxl_p1_reg_t CXL_XSL9_DEF      = {0x0140};
101 static const cxl_p1_reg_t CXL_XSL9_DSNCTL   = {0x0168};
102 static const cxl_p1_reg_t CXL_PSL9_FIR1     = {0x0300};
103 static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
104 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
105 static const cxl_p1_reg_t CXL_PSL9_DEBUG    = {0x0320};
106 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
107 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL  = {0x0350};
108 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
109 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
110 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
111 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
112 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
113 static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
114 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
115 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
116 static const cxl_p1_reg_t CXL_XSL9_ILPP  = {0x0590};
778 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)  in _cxl_p1_addr()
784 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)  in cxl_p1_write()
790 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)  in cxl_p1_read()