479 struct cxl_afu {  struct
480 	struct cxl_afu_native *native;  argument
481 	struct cxl_afu_guest *guest;  argument
482 	irq_hw_number_t serr_hwirq;
483 	unsigned int serr_virq;
484 	char *psl_irq_name;
485 	char *err_irq_name;
486 	void __iomem *p2n_mmio;
487 	phys_addr_t psn_phys;
488 	u64 pp_size;
490 	struct cxl *adapter;
491 	struct device dev;
492 	struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
493 	struct device *chardev_s, *chardev_m, *chardev_d;
494 	struct idr contexts_idr;
495 	struct dentry *debugfs;
496 	struct mutex contexts_lock;
497 	spinlock_t afu_cntl_lock;
500 	atomic_t configured_state;
503 	u64 eb_len, eb_offset;
504 	struct bin_attribute attr_eb;
507 	struct pci_controller *phb;
509 	int pp_irqs;
510 	int irqs_max;
511 	int num_procs;
512 	int max_procs_virtualised;
513 	int slice;
514 	int modes_supported;
515 	int current_mode;
516 	int crs_num;
517 	u64 crs_len;
518 	u64 crs_offset;
519 	struct list_head crs;
543 	struct cxl_afu *afu;  argument