Lines Matching refs:pcr
28 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) in rts5249_get_ic_version() argument
32 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); in rts5249_get_ic_version()
36 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) in rts5249_fill_driving() argument
54 drive_sel = pcr->sd30_drive_sel_3v3; in rts5249_fill_driving()
57 drive_sel = pcr->sd30_drive_sel_1v8; in rts5249_fill_driving()
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, in rts5249_fill_driving()
62 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, in rts5249_fill_driving()
64 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, in rts5249_fill_driving()
68 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) in rtsx_base_fetch_vendor_settings() argument
72 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); in rtsx_base_fetch_vendor_settings()
73 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); in rtsx_base_fetch_vendor_settings()
76 pcr_dbg(pcr, "skip fetch vendor setting\n"); in rtsx_base_fetch_vendor_settings()
80 pcr->aspm_en = rtsx_reg_to_aspm(reg); in rtsx_base_fetch_vendor_settings()
81 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); in rtsx_base_fetch_vendor_settings()
82 pcr->card_drive_sel &= 0x3F; in rtsx_base_fetch_vendor_settings()
83 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); in rtsx_base_fetch_vendor_settings()
85 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); in rtsx_base_fetch_vendor_settings()
86 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); in rtsx_base_fetch_vendor_settings()
87 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); in rtsx_base_fetch_vendor_settings()
89 pcr->flags |= PCR_REVERSE_SOCKET; in rtsx_base_fetch_vendor_settings()
92 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) in rtsx_base_force_power_down() argument
95 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0); in rtsx_base_force_power_down()
96 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0); in rtsx_base_force_power_down()
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0); in rtsx_base_force_power_down()
100 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, in rtsx_base_force_power_down()
103 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); in rtsx_base_force_power_down()
106 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) in rts5249_init_from_cfg() argument
108 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_cfg()
111 if (CHK_PCI_PID(pcr, PID_524A)) in rts5249_init_from_cfg()
112 rtsx_pci_read_config_dword(pcr, in rts5249_init_from_cfg()
115 rtsx_pci_read_config_dword(pcr, in rts5249_init_from_cfg()
119 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); in rts5249_init_from_cfg()
122 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); in rts5249_init_from_cfg()
125 rtsx_set_dev_flag(pcr, PM_L1_1_EN); in rts5249_init_from_cfg()
128 rtsx_set_dev_flag(pcr, PM_L1_2_EN); in rts5249_init_from_cfg()
133 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); in rts5249_init_from_cfg()
137 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); in rts5249_init_from_cfg()
144 static int rts5249_init_from_hw(struct rtsx_pcr *pcr) in rts5249_init_from_hw() argument
146 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_from_hw()
148 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN in rts5249_init_from_hw()
157 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) in rts5249_extra_init_hw() argument
159 struct rtsx_cr_option *option = &(pcr->option); in rts5249_extra_init_hw()
161 rts5249_init_from_cfg(pcr); in rts5249_extra_init_hw()
162 rts5249_init_from_hw(pcr); in rts5249_extra_init_hw()
164 rtsx_pci_init_cmd(pcr); in rts5249_extra_init_hw()
167 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); in rts5249_extra_init_hw()
169 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); in rts5249_extra_init_hw()
171 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); in rts5249_extra_init_hw()
173 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); in rts5249_extra_init_hw()
174 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); in rts5249_extra_init_hw()
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); in rts5249_extra_init_hw()
178 rts5249_fill_driving(pcr, OUTPUT_3V3); in rts5249_extra_init_hw()
179 if (pcr->flags & PCR_REVERSE_SOCKET) in rts5249_extra_init_hw()
180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); in rts5249_extra_init_hw()
182 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); in rts5249_extra_init_hw()
189 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, in rts5249_extra_init_hw()
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, in rts5249_extra_init_hw()
195 return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); in rts5249_extra_init_hw()
198 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) in rts5249_optimize_phy() argument
202 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); in rts5249_optimize_phy()
206 err = rtsx_pci_write_phy_register(pcr, PHY_REV, in rts5249_optimize_phy()
217 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, in rts5249_optimize_phy()
223 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts5249_optimize_phy()
230 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, in rts5249_optimize_phy()
237 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, in rts5249_optimize_phy()
244 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, in rts5249_optimize_phy()
248 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, in rts5249_optimize_phy()
252 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, in rts5249_optimize_phy()
258 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, in rts5249_optimize_phy()
264 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) in rtsx_base_turn_on_led() argument
266 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); in rtsx_base_turn_on_led()
269 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) in rtsx_base_turn_off_led() argument
271 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); in rtsx_base_turn_off_led()
274 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_enable_auto_blink() argument
276 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); in rtsx_base_enable_auto_blink()
279 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) in rtsx_base_disable_auto_blink() argument
281 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); in rtsx_base_disable_auto_blink()
284 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_on() argument
288 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
291 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
293 err = rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
299 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_on()
300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_on()
302 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_on()
304 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_on()
307 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) in rtsx_base_card_power_off() argument
309 rtsx_pci_init_cmd(pcr); in rtsx_base_card_power_off()
310 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, in rtsx_base_card_power_off()
312 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, in rtsx_base_card_power_off()
314 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_card_power_off()
317 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rtsx_base_switch_output_voltage() argument
324 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
331 if (CHK_PCI_PID(pcr, 0x5249)) { in rtsx_base_switch_output_voltage()
332 err = rtsx_pci_update_phy(pcr, PHY_BACR, in rtsx_base_switch_output_voltage()
339 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, in rtsx_base_switch_output_voltage()
345 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); in rtsx_base_switch_output_voltage()
350 rtsx_pci_init_cmd(pcr); in rtsx_base_switch_output_voltage()
351 rts5249_fill_driving(pcr, voltage); in rtsx_base_switch_output_voltage()
352 return rtsx_pci_send_cmd(pcr, 100); in rtsx_base_switch_output_voltage()
355 static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable) in rts5249_set_aspm() argument
357 struct rtsx_cr_option *option = &pcr->option; in rts5249_set_aspm()
360 if (pcr->aspm_enabled == enable) in rts5249_set_aspm()
365 val = pcr->aspm_en; in rts5249_set_aspm()
366 rtsx_pci_update_cfg_byte(pcr, in rts5249_set_aspm()
367 pcr->pcie_cap + PCI_EXP_LNKCTL, in rts5249_set_aspm()
374 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); in rts5249_set_aspm()
377 pcr->aspm_enabled = enable; in rts5249_set_aspm()
447 void rts5249_init_params(struct rtsx_pcr *pcr) in rts5249_init_params() argument
449 struct rtsx_cr_option *option = &(pcr->option); in rts5249_init_params()
451 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; in rts5249_init_params()
452 pcr->num_slots = 2; in rts5249_init_params()
453 pcr->ops = &rts5249_pcr_ops; in rts5249_init_params()
455 pcr->flags = 0; in rts5249_init_params()
456 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; in rts5249_init_params()
457 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
458 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; in rts5249_init_params()
459 pcr->aspm_en = ASPM_L1_EN; in rts5249_init_params()
460 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); in rts5249_init_params()
461 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); in rts5249_init_params()
463 pcr->ic_version = rts5249_get_ic_version(pcr); in rts5249_init_params()
464 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; in rts5249_init_params()
465 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; in rts5249_init_params()
466 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; in rts5249_init_params()
467 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; in rts5249_init_params()
469 pcr->reg_pm_ctrl3 = PM_CTRL3; in rts5249_init_params()
486 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) in rts524a_write_phy() argument
490 return __rtsx_pci_write_phy_register(pcr, addr, val); in rts524a_write_phy()
493 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) in rts524a_read_phy() argument
497 return __rtsx_pci_read_phy_register(pcr, addr, val); in rts524a_read_phy()
500 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) in rts524a_optimize_phy() argument
504 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts524a_optimize_phy()
509 rtsx_pci_write_phy_register(pcr, PHY_PCR, in rts524a_optimize_phy()
512 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
515 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_optimize_phy()
516 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, in rts524a_optimize_phy()
518 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, in rts524a_optimize_phy()
521 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, in rts524a_optimize_phy()
524 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, in rts524a_optimize_phy()
526 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, in rts524a_optimize_phy()
536 rtsx_pci_write_phy_register(pcr, PHY_ANA08, in rts524a_optimize_phy()
543 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) in rts524a_extra_init_hw() argument
545 rts5249_extra_init_hw(pcr); in rts524a_extra_init_hw()
547 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, in rts524a_extra_init_hw()
549 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); in rts524a_extra_init_hw()
550 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, in rts524a_extra_init_hw()
552 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts524a_extra_init_hw()
553 if (is_version(pcr, 0x524A, IC_VER_A)) { in rts524a_extra_init_hw()
554 rtsx_pci_write_register(pcr, LDO_DV18_CFG, in rts524a_extra_init_hw()
556 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts524a_extra_init_hw()
558 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
560 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts524a_extra_init_hw()
562 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts524a_extra_init_hw()
564 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, in rts524a_extra_init_hw()
571 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) in rts5250_set_l1off_cfg_sub_d0() argument
573 struct rtsx_cr_option *option = &(pcr->option); in rts5250_set_l1off_cfg_sub_d0()
575 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); in rts5250_set_l1off_cfg_sub_d0()
580 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); in rts5250_set_l1off_cfg_sub_d0()
581 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); in rts5250_set_l1off_cfg_sub_d0()
594 if (rtsx_check_dev_flag(pcr, in rts5250_set_l1off_cfg_sub_d0()
602 rtsx_set_l1off_sub(pcr, val); in rts5250_set_l1off_cfg_sub_d0()
623 void rts524a_init_params(struct rtsx_pcr *pcr) in rts524a_init_params() argument
625 rts5249_init_params(pcr); in rts524a_init_params()
626 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts524a_init_params()
627 pcr->option.ltr_l1off_snooze_sspwrgate = in rts524a_init_params()
630 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts524a_init_params()
631 pcr->ops = &rts524a_pcr_ops; in rts524a_init_params()
634 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) in rts525a_card_power_on() argument
636 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, in rts525a_card_power_on()
638 return rtsx_base_card_power_on(pcr, card); in rts525a_card_power_on()
641 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) in rts525a_switch_output_voltage() argument
645 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
647 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); in rts525a_switch_output_voltage()
650 rtsx_pci_write_register(pcr, LDO_CONFIG2, in rts525a_switch_output_voltage()
652 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, in rts525a_switch_output_voltage()
659 rtsx_pci_init_cmd(pcr); in rts525a_switch_output_voltage()
660 rts5249_fill_driving(pcr, voltage); in rts525a_switch_output_voltage()
661 return rtsx_pci_send_cmd(pcr, 100); in rts525a_switch_output_voltage()
664 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) in rts525a_optimize_phy() argument
668 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, in rts525a_optimize_phy()
673 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, in rts525a_optimize_phy()
678 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, in rts525a_optimize_phy()
682 if (is_version(pcr, 0x525A, IC_VER_A)) in rts525a_optimize_phy()
683 rtsx_pci_write_phy_register(pcr, _PHY_REV0, in rts525a_optimize_phy()
690 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) in rts525a_extra_init_hw() argument
692 rts5249_extra_init_hw(pcr); in rts525a_extra_init_hw()
694 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); in rts525a_extra_init_hw()
695 if (is_version(pcr, 0x525A, IC_VER_A)) { in rts525a_extra_init_hw()
696 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, in rts525a_extra_init_hw()
698 rtsx_pci_write_register(pcr, RREF_CFG, in rts525a_extra_init_hw()
700 rtsx_pci_write_register(pcr, LDO_VIO_CFG, in rts525a_extra_init_hw()
702 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, in rts525a_extra_init_hw()
704 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, in rts525a_extra_init_hw()
706 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, in rts525a_extra_init_hw()
708 rtsx_pci_write_register(pcr, OOBS_CONFIG, in rts525a_extra_init_hw()
731 void rts525a_init_params(struct rtsx_pcr *pcr) in rts525a_init_params() argument
733 rts5249_init_params(pcr); in rts525a_init_params()
734 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; in rts525a_init_params()
735 pcr->option.ltr_l1off_snooze_sspwrgate = in rts525a_init_params()
738 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; in rts525a_init_params()
739 pcr->ops = &rts525a_pcr_ops; in rts525a_init_params()